Search

In this paper, two essential components of the Flash ADC are designed and integrated within a new Flash ADC architecture. The power consumption is reduced by realizing a switched-capacitor positive feedback (SCPF) comparators structure as a replacement for conventional comparators structure. The SCPF comparator is tailored to a single-ended input/single-ended output configuration that operates in two steps: offset-cancelation function followed by comparison decision. Furthermore, the encoding stage is implemented using N parallel independent components of one single AND gate each, where N is the number of quantized regions. This structure provides fast encoding with minimal encoding activities. The design architecture exploits two stages, which are separated by latches. The first stage allocates the analog input to a quantized region, while the second stage converts the level of the quantized region into its corresponding binary code. This separation is considered the key success for incorporating the SCPF comparators structure into our Flash ADC architecture. HSPICE simulations of the proposed design use 35 nm Synopsys FinFet technology and 1-V power supply. The simulation results show that our 5-bit Flash ADC can function at a sampling frequency of up to 1 GHz, with an input signal of 500 MHz at Nyquist rate, where the amplitude input signal is ranging from 0.2 to 0.8 V with an overall maximum power consumption of 3 mW. [ABSTRACT FROM AUTHOR]