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This paper reports on the integration of MOCVD SBT based stacked ferroelectric capacitors in a 0.35 μm CMOS technology for embedded FeRAM, using a ferroelectric capacitor (FeCap) that is scalable to a 3D configuration. The electrical parameters of the CMOS devices with and without FeCap integration are presented. No significant shifts of the CMOS characteristics are noticed after FeCap integration. Also the effects of the CMOS processing on the FeCaps are discussed. There is no degradation of the hysteresis loops of the FeCaps throughout the CMOS back-end-of-line processing, which proves that the integrated encapsulation layer effectively prevents any hydrogen induced damage. Another key element in the successful integration of stacked ferroelectric devices is the conductive oxygen barrier, which protects the plugs from oxidation. A low contact resistance and a high yield are obtained on plug contacts covered by the oxygen barrier. Also damage free etching is a critical issue in FeRAM integration. Excellent results are presented for the etch process to form the contacts to the electrodes. [ABSTRACT FROM AUTHOR]

Abstract: In this work, the difficult scaling of FeRAM is circumvented by fabricating 3-dimensional ferroelectric capacitors stacked on W plugs and successfully integrated in 0.18μm technology using MOCVD SBT. The effective remnant polarization was increased by 70% due to the sidewall contribution. Also, high reliability of 3-D capacitors was assessed. The samples showed no fatigue degradation after 1013 ±5V cycles. From extrapolation of both imprint and retention results, a wide sensing window is kept after 10 years in most severe temperature condition, that is at 150°C. Critical integration issues are discussed for further scaling in 0.13μm technology and below. [Copyright &y& Elsevier]