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The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise) signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator's circuit. This article presents the results of a CMOS comparator with hysteresis design -- the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC. [ABSTRACT FROM AUTHOR]

In this paper, two LC Voltage-Controlled Oscillators (LC-LCVCO1 and LC-VCO2) are designed using TSMC 65 nm LP/MS/ RF CMOS technology. Two arrays, one of which is a 6-bit capacitor array and the other -- an array of MOS varactors, provide a wide LC-VCO frequency tuning range. Post-layout simulation results unveiled that at 1.8 V supply voltage the tuning range of LC-VCO1 spans from 5.17 GHz to 6.76 GHz and for LC-VCO2 the range spans from 6.33 GHz to 8.08 GHz. The phase noise at 1 MHz offset frequency is about -123.1 dBc/Hz for LC-VCO1 and -121.6 dBc/Hz for LC-VCO2. The power dissipation at maximum carrier is 30.47 mW for LC-VCO1 and 30.5 mW for LC-VCO2. The layout area is 285x335 μm and 255x305 μm, respectively for LC-VCO1 and LC-VCO2. [ABSTRACT FROM AUTHOR]