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In this article, a moving accumulative sign filter (MASF) voter model and a low-power serial voting circuit are proposed for high-speed clock data recovery (CDR). Different from the previously reported parallel voter and moving average majority voter (MV), the proposed design is based on the MASF algorithm and adopts a two-stage voting structure. Only D-flip-flop (DFF) and basic logic gates are used to realize the serial voting function of the four continuous lead/lag/hold decision signals. The proposed MV realizes the signal processing of the four-phase error information without using traditional gain and quantization operations. In addition, by eliminating the redundant output state, the input noise of the digital filter of CDR can be reduced, which could also reduce the power consumption of the subsequent circuits due to less logical flips. As a result, the proposed serial MV can operate at a half baud rate in a high-speed CDR and it can reduce the chip area by removing the demultiplexer unit and the moving average filter. The proposed MV circuit is implemented for a high-speed CDR using a 40-nm CMOS process, which shows a 12-GHz maximum operating speed. The measured power consumption of the whole voter at 10 GHz is only 0.55 mW and the core chip area is $8.6\,\times \,25.4\,\,\mu \text{m}^{2}$. [ABSTRACT FROM AUTHOR]

This paper presents a high linear dynamic range light-to-frequency converter (LFC) with integrated photodiodes (PDs). The high dynamic range with linear response is achieved by two techniques. At first, the NWell/PSubstrate PD is regulated to almost zero voltage drop, in order to minimize the bias-dependent leakage current under a low light irradiance. Secondly, a replica amplifier is implemented to monitor the offset voltage of the regulator against process-voltage-temperature variation. As the result, the systematic and layout-dependent input offset voltage of the regulator can be reduced. The proposed LFC chip is fabricated using 0.35- \mu \textm 2-poly-3-metal nonepitaxy CMOS technology with a die size of $1.02\times 0.83$ mm2. According to the measurement results, the proposed LFC is much less sensitive to temperature variation and it exhibits more than six orders of magnitude linear response under the light irradiance as low as 0.5 nW/cm2 with a temperature range from −25 °C to 125 °C. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power column-parallel inverter-based cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuit. By partially floating the capacitors inside the multiply digital-analog-converter during the least significant bit (LSB) quantization, the amplifier load capacitance could be significantly scaled down, which allows much higher settling speed and shorter cycle period. Since the signal-to-noise ratio for LSB cycle is relaxed due to the residual amplification, the proposed capacitance scaling only contributes ignorable input-referred quantization noise. Using the proposed techniques, a cyclic ADC can operate under 50% power consumption without suffering conversion rate, noise performance, and linearity. A 12-b quantization resolution test chip is fabricated using the TSMC 0.18- \mu \textm technology with 110 column-parallel ADC channels and 10.08- \mu \textm \times 750 - \mu \textm column pitch. The 3.5/−2 LSBs integral nonlinearity and 10.1-b effective-number-of-bit are measured under 2- \mu \texts sampling rate with 120- \mu \textW power consumption per channel. [ABSTRACT FROM AUTHOR]

A compact voltage-mode bandgap voltage reference (BGR) is presented. Instead of using overhead circuits, the silicon bandgap narrowing effect is exploited for bipolar junction transistor’s (BJT) curvature reduction and residual curvature correction. Prototype measurements in a 0.18- \mu \textm standard CMOS process show that the curvature of the BJT is effectively reduced from its inherent 3.6 mV to 1.4 mV. The proposed BGR measures a minimum temperature coefficient of 8.7 ppm/ °C from −55 °C to 125 °C by batch trimming one resistor. After a curvature trimming, it further improves to 4.1 ppm/ °C. The BGR has a minimum supply voltage of 1.3 V, 4.3 \mu \textA nominal current consumption, 0.03%/V line sensitivity, and 2 mV/mA load sensitivity at 25 °. The output rms noise in the $0.1\sim 10$ -Hz band measures 10.23 \mu \text{V} . [ABSTRACT FROM PUBLISHER]

Abstract: In this paper, we propose a pseudo dynamic buffer (PDB) for footed domino logic circuit implementation. Using the proposed PDB structure, the output pulse during the precharge process is prevented from propagating to the output stage, as is the case in conventional case. As a result, up to half of the power is saved compared to a conventional domino gate, while improving the sampling window of the dynamic gate. This PDB structure is applicable not only for Pull-down network (N-type) dynamic logic, but also for Pull-up networks (P-type). Simulation results illustrate improved performance using the proposed scheme compared to the conventional dynamic logic for different loading conditions, clock frequencies and logic functions. In addition, our proposed design reduces the clock loading from conventional three to two transistors. As a result, the proposed scheme significantly saves power due to lower load capacitance on the clock bus. Test structures are fabricated in CMOS technology. Measurement results validate the proposed concept and illustrate power saving as compared to conventional design. [Copyright &y& Elsevier]

Abstract: In this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circuit design. Compared to using three clock transistors in the conventional TSPC-based scheme, the proposed circuit only requires two transistors. As a result, the clock load capacitance is reduced, leading to low power consumption in the clock distribution network. A keeper design to solve charge sharing is also demonstrated. Simulation results using 90nm and 45nm CMOS technologies are provided and iscussed, respectively, which illustrate power saving as compared to conventional design not only when the input logic is active but also when the input logic is held to zero. [Copyright &y& Elsevier]

The concept of compressive acquisition image sensor is to compress data while sensing and prior to storage. In this paper, the concept of compressive acquisition image sensor is developed, implemented and experimentally validated for both spatial and temporal domains. In the proposed scheme, the image sensor array is divided into quadrants integrating logic circuitry which performs online spatial compression of the raw data prior to storage. The quadrants are subsequently further classified into background/non-background quadrants by an off-array judge logic which enables to adaptively track the associated temporal information. Temporal redundancy between frames is hence removed in the readout phase. The proposed compressive acquisition algorithm is simulated and experimentally validated for both spatial and temporal domains through a hardware prototype. Experimental results show that the proposed algorithm enables more than 50% memory saving at a PSNR level of 26 dB with around 0.5 BPP. This result not only greatly reduces the memory requirements for a digital pixel CMOS image sensor, but also results in area saving as data is only stored after being compressed. [ABSTRACT FROM AUTHOR]

In this paper, we present a 4T low-power linear-output current-mediated CMOS APS imager, in which reset and read-out operations are carried-out simultaneously on two pixels of the same row. The proposed operating technique greatly simplifies the pixel architecture with only four transistors and two control signals required, while six transistors and four control lines are required by its current-mediated counterpart. The imager achieves fixed pattern noise (FPN) correction during pixel-readout and exhibits a power consumption which is independent of the imager array size, since only a single current source is solicited at any given time due to the array-level operating technique. A linearization circuit technique using the transistor's channel length modulation effect is employed enabling to double the linear range of the pixel's photon-to-output signal transfer function. Performance analysis and experimental results are presented for a 32\,\times\,32 image sensor array prototype, fabricated using AMS 0.35-\mum process. The pixel size is 6.5\,\times\,6.5 \mu\ m^2 with 22% fill-factor. The chip total power consumption is less than 1 mW, at 50 frames/s with a 3.3 V power supply. [ABSTRACT FROM AUTHOR]

This paper presents the architecture, algorithm, and VLSI hardware of image acquisition, storage, and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with nondestructive storage capability using 8-bit Static-RAM device embedded at the pixel level. The pixel-level memory is used to store the uncompressed illumination data during the integration mode as well as the compressed illumination data obtained after the compression stage. An adaptive quantization scheme based on fast boundary adaptation rule (FBAR) and differential pulse code modulation (DPCM) procedure followed by an online, least storage quadrant tree decomposition (QTD) processing is proposed enabling a robust and compact image compression processor. A prototype chip including 64 \times 64 pixels, read-out and control circuitry as well as an on-chip compression processor was implemented in 0.35 \mum CMOS technology with a silicon area of 3.2 \times\, \ 3.0 mm^2 and an overall power of 17 mW. Simulation and measurements results show compression figures corresponding to 0.6–1 bit-per-pixel (BPP), while maintaining reasonable peak signal-to-noise ratio levels. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel energy harvesting technique based on an asynchronous pixel structure and an efficient energy generation scheme, referred to as avalanche energy generation (AEG). The key idea behind using an asynchronous type of pixel is to lower the power consumption by enabling only active pixels to be read-out after which they enter into a power generation mode. In this mode, the on-pixel photodetector itself will be used to harvest the light energy from the environment and make it available to active pixels. A very interesting feature about our proposed approach is that during a frame capture, critical energy is mainly required for starting-up activity. Once a group of pixels have been read-out, the available energy will rise and more array activity will contribute to the generation of more energy, hence creating an avalanche effect. In contrast to other early designs of energy harvesting image sensors, our scheme uses the photodetector itself for power generation. This results in better utilization of the photosensitive area and more importantly an improved energy generation scheme. Detailed power analysis and extensive simulation results are provided in this paper, which validate the proposed concept. Three test structures have been fabricated in AMIS 1-poly, 5-metal CMOS 0.35-\mum n-well process. The power generation process and event generation have been successfully verified experimentally. [ABSTRACT FROM AUTHOR]

An ultra-low power embedded CMOS temperature sensor based on serially connected subthreshold MOS operation is implemented in a 0.18 µm CMOS process for passive RFID food monitoring applications. Employing serially connected subthreshold MOS as sensing element enables reduced minimum supply voltage for further power reduction, which is of utmost importance in passive RFID applications. Both proportional-to-absolute-temperature (PTAT) and complimentary- to-absolute-temperature (CTAT) signals can be obtained through proper transistor sizing. With the sensor core working under 0.5 V and digital interfacing under 1 V, the sensor dissipates a measured total power of 119 nW at 333 samples/s and achieves an inaccuracy of + 1/-8 °C from -10 °C to 30 °C after calibration. The sensor is embedded inside the fabricated passive UHF RFID tag. Measurement of the sensor performance at the system level is also carried out, illustrating proper sensing operation for passive RFID applications. [ABSTRACT FROM AUTHOR]

In this paper, a new design paradigm referred to as compressive acquisition CMOS image sensors is introduced. The idea consists of compressing the data within each pixel prior to storage, and hence, reducing the size of the memory required for digital pixel sensor. The proposed compression algorithm uses a block-based differential coding scheme in which differential values are captured and quantized online. A time-domain encoding scheme is used in our CMOS image sensor in which the brightest pixel within each block fires first and is selected as the reference pixel. The differential values between subsequent pixels and the reference within each block are calculated and quantized, using a reduced number of bits as their dynamic range is compressed. The proposed scheme enables reduced error accumulation as full precision is used at the start of each block, while also enabling reduced memory requirement, and hence, enabling significant silicon area saving. A mathematical model is derived to analyze the performance of the algorithm. Experimental results on a field-programmable gate-array (FPGA) platform illustrate that the proposed algorithm enables more than 50% memory saving at a peak signal-to-noise ratio level of 30 dB with 1.5 bit per pixel. [ABSTRACT FROM AUTHOR]

Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression processing unit are reviewed, followed by systems that integrate focal-plane compression. The paper also provides a thorough review of a new design paradigm, in which image compression is performed during the image-capture phase prior to storage, referred to as compressive acquisition. High-performance sensor systems reported in recent years are also introduced. Performance analysis and comparison of the reported designs using different design paradigm are presented at the end. [ABSTRACT FROM AUTHOR]

This letter presents a compensation topology which minimizes the inter-/intra-die spread and proportional-to-absolute-temperature (PTAT) drift of the base–emitter voltage ( V\text {be} ) of a bipolar junction transistor (BJT). Without using special devices, the base recombination current from a deep-saturated BJT is utilized in this scheme. Before compensation, the V\text {be} standard deviation (STD) of 15 standalone BJTs measures 3.24 mV at 25 °C with constant external bias currents. After compensation, V\text {be} STD of 30 dies from two batches reduces to 1.8 mV with on-chip bias current. The PTAT drift of V\text {be} as that in typical BJT-based designs are also alleviated. [ABSTRACT FROM PUBLISHER]

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm 2 . At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents a time-to-first spike (TFS) and address event representation (AER)-based CMOS vision sensor performing image capture and on-chip histogram equalization (LIE). The pixel values are read-out using an asynchronous handshaking type of read-out, while the HE processing is carried out using simple and yet robust digital timer occupying a very small silicon area (0.1 × 0.6 mm2). Low-power operation (10 nA per pixel) is achieved since the pixels are only allowed to switch once per frame. Once the pixel is acknowledged, it is granted access to the bus and then forced into a stand-by mode until the next frame cycle starts again. Timing errors inherent in AER-type of imagers are reduced using a number of novel techniques such as fair and fast arbitration using toggled priority (TP), higher-radix, and pipelined arbitration. A verilog simulator was developed in order to simulate the effect of timing errors encountered in AER-based imagers. A prototype chip was implemented in AMIS 0.35 μm process with a silicon area of 3.1 × 3.2 mm2. Successful operation of the prototype is illustrated through experimental measurements. [ABSTRACT FROM AUTHOR]

Gaussian mixture models (GMM)-based classifiers have shown increased attention in many pattern recognition applications. Improved performances have been demonstrated in many applications, but using such classifiers can require large storage and complex processing units due to exponential calculations and a large number of coefficients involved. This poses a serious problem for portable real-time pattern recognition applications. In this paper, first the performance of GMM and its hardware complexity are analyzed and compared with a number of benchmark algorithms. Next, an efficient digital hardware implementation is proposed. A number of design strategies are proposed in order to achieve the best possible tradeoffs between circuit complexity and real-time processing. First, a serial-parallel vector-matrix multiplier combined with an efficient pipelining technique is used. A novel exponential calculation circuit based on a linear piecewise approximation is proposed to reduce hardware complexity. The precision requirement of the GMM parameters in our classifier are also studied for various classification problems. The proposed hardware implementation features programmability and flexibility offering the possibility to use the proposed architecture for different applications with different topologies and precision requirements. To validate the proposed approach, a prototype was implemented in 0.25-µm CMOS technology and its operation was successfully tested for gas identification application. [ABSTRACT FROM AUTHOR]

A CMOS digital pixel sensor (DPS) with programmable resolution and reconfigurable conversion time is described. The chip features a unique architecture based on the pulse width modulation (PWM) technique and operates with either an 8-b or 4-b accuracy. The 8-b conversion mode is used for high-precision imaging while the 4-b conversion mode provides a shorter conversion time and a two times increase in spatial resolution. Two quantization schemes are studied, namely, the uniform and the nonuniform time-domain quantizers, which are referred to as UQ and NUQ, respectively. It is shown that the latter scheme not only permits to linearize the nonlinear response of the PWM sensor, but also allows to significantly speed up the conversion time, particularly for wide dynamic range and low coding resolutions. A prototype of 32 x 32/64 x 32 pixels has been fabricated using 1-poly, 5-metal CMOS 0.35-μm n-well standard process. Power dissipation is 10 mW at VDD = 3.3 V, dynamic range is 90 dB, while dark current was measured at 1 pA. The reconfiguration features of the chip have been verified experimentally. [ABSTRACT FROM AUTHOR]

This paper presents a digital pixel sensor (DPS) array employing a time domain analogue-to-digital conversion (ADC) technique featuring adaptive dynamic range and programmable pixel response. The digital pixel comprises a photodiode, a voltage comparator, and an 8-bit static memory. The conversion characteristics of the ADC are determined by an array-based digital control circuit, which linearizes the pixel response, and sets the conversion range. The ADC response is adapted to different lighting conditions by setting a single clock frequency. Dynamic range compression was also experimentally demonstrated. This clearly shows the potential of the proposed technique in overcoming the limited dynamic range typically imposed by the number of bits in a DPS. A 64 × 64 pixel array prototype was manufactured in a 0.35-μm, five-metal, single poly, CMOS process. Measurement results indicate a 100 dB dynamic range, a 41-s mean dark time and an average current of 1.6 μA per UPS. [ABSTRACT FROM AUTHOR]

A novel ultra-low power operating technique is presented for Mega-pixels current-mediated CMOS imagers. In the proposed technique, the reset and read-out phases occur simultaneously: as a single pixel is being read-out another pixel is being reset Such a strategy reduces power consumption by more than 2 orders of magnitude for current- mediated Mega-pixels CMOS imagers, while still allowing for on-read-out fixed pattern noise correction. Power consumption becomes independent of both read-out speed and imager array size. Additionally, the proposed operating technique leads to improved linearity for the pixel response, increased dynamic range as well as on-chip digital shutter functionality. A single additional address decoder is required to generate the reset signals, resulting in a marginal increase in silicon area. The wiring overhead is kept to a minimum with only a single control signal required to operate the current- mediated CMOS imager. [ABSTRACT FROM AUTHOR]

In this paper we propose an on-pixel Analogue-to-Digital Converter (ADC) based on pulse frequency modulation (PFM) scheme. This PFM based converter presents a viable solution for pixel-level based ADC. It uses a simple and robust circuit that can be implemented in a compact area resulting in a 23% fill-factor for a digital vision sensor in 0.25 μm CMOS technology. An in-built light adaptation mechanism has also been implemented which allows the sensor to better adapt to low-light intensity or to adjust the sensor saturation level. As a consequence, the proposed sensor features a programmable dynamic range. Image lag is eliminated since a reset of the photodetector is performed after the conversion period. A prototype comprising a 32×32 pixel array has been implemented in CMOS 0.25 μm technology. Each pixel occupies an area of 45×45 μm2 with an average power consumption of 85 μW per pixel. [Copyright &y& Elsevier]

In this letter, a pulse-width modulated digital pixel sensor is presented along with its inherent advantages such as low power consumption and wide operating range. The pixel, which comprises an analog processor and an 8-bit memory cell, operates in an asynchronous self-resetting mode. In contrast to most CMOS image sensors, in our approach, the photocurrent signal is encoded as a pulse-width signal, and converted to an 8-bit digital code using a Gray counter. The dynamic range of the pixel can be adapted by simply modulating the clock frequency of the counter. To test the operation of the proposed pixel architecture, an image sensor array has been designed and fabricated in a 0.35-µm CMOS technology, where each pixel occupies an area of 45 × 45 µm². Here, the operation of the sensor is demonstrated through experimental results. [ABSTRACT FROM AUTHOR]

In this letter, a compact reconfigurable counter memory (RCM) is proposed for spiking pixels. In contrast to conventional in-pixel counter circuitry, the proposed RCM does not rely on a flip-flop-based circuit but instead uses a very novel circuit structure that combines a combinational incrementer together with static and dynamic memory cells. The proposed RCM provides counting as well as in-pixel storage functionalities allowing for intermediate readout of digital pixel values. Reported experimental results validate the novel concept of RCM-based spiking pixel in AMIS 0.35-µm CMOS technology. The proposed pixel architecture is inherently insensitive to power supply voltage scaling and is thus well suited to submicrometer CMOS processes. [ABSTRACT FROM AUTHOR]

In this paper, a ZnO hierarchical nanostructure based gas sensor is presented. The proposed implementation features short response/recovery time and ultra-high output response at room temperature (RT). In order to take the advantages of complementary-metal-oxide-semiconductor (CMOS) process in terms of miniaturization and cost-effectiveness, a novel fabrication recipe, consisting of CMOS-compatible techniques, is proposed to form a patterned triple-layer metal, which functions as both interconnection electrodes and catalyst for our reported ZnO hierarchical nanostructure. This enables rapid and local growth of ZnO hierarchical nanostructure directly on a single silicon chip. Reported peak RT output response of 32 (20 ppm NO 2 ) provides a significant 28-fold improvement over the traditional widely adopted nanowire-based gas sensor. Meanwhile, a time efficient gas sensor is also validated by the presented temporal performance with a response and recovery time of 72 s and 69 s, respectively. In addition, compared with the previously demonstrated gas sensors operating at 200–300 °C, the proposed RT sensing completely removes the power-hungry heater and eliminates the related thermal reliability issues. Moreover, the demonstrated process flow well addresses the challenging issues of the traditional mainstream “drop-cast” method, including poor yield, non-uniformity of device performance and low efficiency caused by inevitable manual microscope inspection. [ABSTRACT FROM AUTHOR]