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Highlights: [•] Low frequency noise and its variability through CMOS planar bulk technologies. [•] Evolution with technology generation of oxide trap density as a function of EOT. [•] Improvement of LFN statistical variability with decrease of EOT. [Copyright &y& Elsevier]

Abstract: A detailed characterization and modeling of the low frequency noise in a CMOS inverter is presented for the first time. A low frequency noise model for the load current and the output voltage is developed based on the carrier number fluctuations scheme. This model allows obtaining a consistent description of the noise characteristics of CMOS inverters issued from a 45nm bulk CMOS technology. It should constitute a reliable theoretical framework for further analysis of the impact of time fluctuations on the static and dynamic operation of CMOS inverter based circuits. [Copyright &y& Elsevier]

Low-frequency noise (LFN) of high-k/metal stack nMOS and pMOS transistors is experimentally studied. Results obtained on 32-nm complementary metal–oxide–semiconductor (CMOS) technologies, including LFN spectra and normalized power spectral density data analysis, are presented. These results indicate that the carrier number fluctuation is the main noise source for both nMOS and pMOS devices. As noise performance may strongly vary between different devices on one chip, the variability of the LFN when scaling down devices was also evaluated. A model known in the literature was used and enhanced in order to understand the noise level variability. A statistical analysis of the noise variability is also presented showing the dependence of the standard deviation with the device area. The comparison with former results from 45-nm poly/SiON technology demonstrates a better control of noise variability in the 32-nm CMOS technology. [ABSTRACT FROM PUBLISHER]

In this letter, we demonstrate the existence of the source–drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on $Y$ -function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices. [ABSTRACT FROM AUTHOR]

The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed. [ABSTRACT FROM AUTHOR]

The impact of dynamic variability due to low-frequency fluctuations on the operation of CMOS inverters, which constitute the basic component of SRAM cell, is investigated. The experimental methodology to characterise the effect of dynamic variability in a CMOS inverter is first established based on fast I-V measurements of the load current following the application of a ramp input voltage Vin(t). It is shown that, for small ramp rise times, the load current characteristics IDD(Vin) exhibit a huge sweep-to-sweep dispersion due to low-frequency noise. The impact of such dynamic variability sources on the inverter's output characteristics Vout(Vin) is finally demonstrated, revealing a 20% noise margin reduction for the smallest inverter cell. [ABSTRACT FROM AUTHOR]