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Angular single-event (SE) mechanisms and experimental upset data for 14-/16-nm bulk fin field-effect transistor (FinFET) technologies are presented and analyzed. The discrete structure of FinFETs introduces unique geometrical and orientation dependences for angular SE mechanisms and SE upset (SEU) responses of FinFET circuits. Geometric analyses and 3-D technology computer-aided design results effectively explain the angular mechanisms behind experimentally observed SE crosssectional responses. Results show that angular SEU crosssectional characteristics can be attributed to the proportional contributions of charge deposition regions in the fin structure and the subfin bulk substrate. [ABSTRACT FROM PUBLISHER]

A new error correction circuit (ECC) for delay-locked loops (DLLs) using combinational logic and a “peeled” voltage-controlled delay line (VCDL) layout is proposed. The ECC can be used to mitigate missing output pulses due to single-event effects in scaled CMOS processes. The implementation of the ECC results in no significant area penalty or performance degradation of the DLL. Simulations at LETs up to 100~\MeV\-\cm^2/\mg show that the ECC mitigates missing pulses in DLLs fabricated at features sizes down to 40 nm and operating frequencies up to 1 GHz. In addition, any ion strike within the error correction logic components will have no significant impact on the DLL output signal. Emulated results obtained through an FPGA implementation of the ECC demonstrate the effectiveness and portability of the hardening technique. [ABSTRACT FROM PUBLISHER]

A novel “quad-path” radiation hardening technique is implemented in a switched-capacitor sample/hold amplifier and validated by laser testing. The proposed technique eliminates the signal-range limitations of the original dual-path hardening technique by using both n- and p-type switches with separate dual and complementary signal paths. Single-event effect sample errors are reduced by up to 90%, with minimal speed, power and area penalties. [ABSTRACT FROM PUBLISHER]

Negative bias temperature instability has been experimentally demonstrated to increase the cross-section of the single event response for 40 nm flip-flops. Analysis on the underlying mechanisms, including threshold voltage shift, is presented. [ABSTRACT FROM AUTHOR]

Perturbations in N-well potential have been shown to strongly affect the charge collection, charge sharing, and parasitic bipolar transistor characteristics. In this paper, temporal and spatial characteristics of the well-potential modulation are characterized through 3-D TCAD simulations. Effects of well-contact layout, ion energy, and technology process parameters for a 90-nm bulk CMOS process are investigated. [ABSTRACT FROM PUBLISHER]

Heavy-ion experiments on spatially isolated inverters and densely populated inverters demonstrate the effects of transistor density on single-event (SE) transients in bulk CMOS. Increased transistor density reduces SE cross section dramatically while having little impact on transient pulse width. [ABSTRACT FROM PUBLISHER]

Mixed mode TCAD simulations are used to show the effects of guard bands and high density well contacts in maintaining the well potential after a single event strike and thus reduce the width of long transients in a 130-nm CMOS process. Experimental verification of the effectiveness in mitigating long transients was achieved by measuring the distribution of SET pulse widths produced by heavy ions for circuits with isolated contacts and for circuits with guard bands combined with larger contacts in a 130-nm process using an autonomous characterization technique. Heavy-ion test results indicate that controlling the well potential by using guard bands, along with high density well contacts, helps eliminate of SETs longer than 1 ns. [ABSTRACT FROM PUBLISHER]