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To enable heterogeneous integration of InGaAs based transistors with Si complementary metal-oxide-semiconductor (CMOS) devices, metal contacts to n+-InGaAs need to have high thermal stability for CMOS process compatibility and ultra-low contact resistance to achieve good device performance. In this work, n+-InGaAs contacts with ultra-low contact resistivity pc based on refractory metals such as molybdenum (Mo) were realized. Use of refractory metal contacts achieves good thermal stability. An improved process that eliminates oxide between the metal and n+-InGaAs by using an in situ Ar+-plasma treatment prior to metal deposition achieves ultra-low pc. Furthermore, a nano-scale transmission line method (nano-TLM) structure with significantly reduced parasitic leakage was designed and fabricated to improve the pc extraction accuracy. The improved test structure introduces a SiO2 isolation layer between Mo and InGaAs outside the active or mesa region to eliminate a parallel leakage path that is present in other nano-TLM structures reported in the literature. [ABSTRACT FROM AUTHOR]

We report on the growth of In0.30Ga0.70As channel high electron mobility transistor (HEMT) epi-layers on a 200-mm Si substrate by metal-organic-chemical-vapor-deposition. The HEMT layers were grown on the Si substrate by using a ~3- \mu \textm thick epitaxial buffer composing of a Ge layer, a GaAs layer, and a compositionally graded and strain relaxed InAlAs layer. The optimized epitaxy has a threading dislocation density of less than 2 \times 10^7 cm−2 and a root mean square surface roughness of ~6.7 nm. The device active layers include a \delta -doped InAlAs bottom barrier, a ~15-nm thick InGaAs channel, a ~8-nm InGaP top barrier layer and a heavily doped InGaAs contact layer. MOSHEMTs with channel length down to 130 nm were fabricated. The devices achieve a peak transconductance of \sim 450 ~\mu \textS/ \mu \textm at V D of 0.5 V. The peak effective mobility ( \mu \text {eff} ) in a device with a channel length of 20 \mu \textm device channel was ~3700 cm2/ \textV \cdot \texts . [ABSTRACT FROM AUTHOR]

Integration of InxGa1–xAs n-MOSFETs and SiyGe1–y p-MOSFETs could be a key to realize future low-power and high-speed logic circuits. In this paper, monolithic integration of InAs n-MOSFETs and Ge p-MOSFETs on a Si substrate is reported. To address the challenge of integrating materials with large lattice mismatch (InAs and Ge on Si substrate), a sub-120-nm GaSb-on-GaAs buffer on a germanium-on-insulator (GeOI) starting substrate is employed. The strain resulting from the 7.78% lattice mismatch between the GaSb and GaAs layers is mainly relaxed via interfacial misfits at the GaSb/GaAs interface, enabling significant reduction in the buffer thickness. For device fabrication, a self-aligned gate last process flow with Si-CMOS-compatible modules is used. To realize raised source-drain device architecture, a combination of dry and digital etch processes is developed to etch InAs and Ge cap layers. Devices with channel thicknesses less than 5 nm and channel lengths less than 200 nm are realized for both n- and p-MOSFETs, with promising electrical characteristics. [ABSTRACT FROM PUBLISHER]