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This paper presents a novel frequency compensation scheme for the stability of low dropout regulator (LDO). The proposed compensation scheme introduces a zero in the voltage regulation loop to enlarge gain and phase margin at high‐frequencies. As a result, high open‐loop‐gain and improved load regulation performances are achieved, and a particular resistor is introduced in the compensation structure to cancel the voltage drop originating from cable resistances at the output to further improve the load regulation performance. The proposed LDO with wide input/output range and high‐power supply rejection is designed and implemented in a 180 nm CMOS process. The LDO operates with an input voltage range of 4–16 V, an output voltage range of 1.5–5 V and an output current range of 0–1000 mA. High open loop gain and high bandwidth are achieved, and the simulated performances of load regulation and line regulation are less than 32 μV/mA and less than 3 mV/V over the whole operation range, respectively. The on‐chip compensation capacitor required by the compensation module is only 1.8 pF. © 2023 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

This article presents an energy-efficient BJT-based temperature sensor. The output of sensing front-ends is modulated by employing an incremental Δ - Σ ADC as a readout interface. The cascoded floating-inverter-based dynamic amplifier (FIA) is used as the integrator instead of the conventional operational transconductance amplifier (OTA) to achieve a low power consumption. To enhance the accuracy, chopping and dynamic element matching (DEM) are applied to eliminate the component mismatch error while β -compensation resistor and optimized bias current are used to minimize the effect of β variation. Fabricated in a standard 180-nm CMOS process, this sensor has an active area of 0.13 mm 2 . While dissipating only 45.7 μ W in total, the sensor achieves an inaccuracy of ±0.8 °C (3 σ) from −50 °C to 150 °C after one-point calibration. [ABSTRACT FROM AUTHOR]

Abstract: Si n–i–p tunnel field-effect transistor (TFET) fabricated by plasma implantation and laser annealing is proposed. This TFET has sharp lateral source doping profile, which can reduce the tunneling distance and improve carrier tunneling. Enhanced on-current (12μA/μm) and improved I ON/I OFF ratio (6×106) are observed in this TFET [V DS =(V GS − V BTBT)=−1.1V; V BTBT is the V GS at the lowest subthreshold current observed at given V DS] at T =300K. In addition, the TFET fabricated by laser annealing shows improved subthreshold characteristics, reduced tunneling resistance and smaller threshold voltage than TFET fabricated by rapid thermal annealing. Low-temperature measurements of this TFET were also performed to confirm the carrier injection mechanism of band-to-band tunneling. Plasma implantation and laser annealing are effective and suitable to be applied in current CMOS technology for low power devices. [Copyright &y& Elsevier]

To reduce the power consumption and improve the device performance in scaled CMOS integrated circuits, transistors with steep subthreshold swing (SS) is highly desirable. The tunnel field-effect transistor (TFET) based on the band-to-band tunneling has been suggested as a replacement to conventional MOSFETs. In order to improve the device performance of TFET, enhanced carrier transport across the tunneling junction is crucial. In this paper, source-pocket Si TFET is presented and successfully fabricated by laser annealing. This TFET has enhanced lateral electric field across the source tunneling junction, resulting in a reduction of tunneling distance. The experimental data of the proposed paper, for the first time, shows steep SS (46 mV/dec at 1 \pA/\mu\m), excellent ION/IOFF ratio (<\10^7), and improved output characteristics at T = \300\ \K due to the dramatic reduction of the tunneling resistance. Compared with other TFET works, the proposed method is efficient to improve the device performance on TFET. [ABSTRACT FROM AUTHOR]