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A low-power IEEE 802.15.4z high-rate PHY (HRP) compatible coherent transmitter is described. The proposed transmitter uses a digital polar architecture with fixed amplitude steps in the power amplifier and asynchronous time-discrete pulse shaping. The pulse-shaping unit consists of a finite-impulse response (FIR) filter using current-starved inverter-based delay taps that can be calibrated on-chip. An injection-locked ring oscillator (ILRO)-based frequency synthesis enables wideband operation from 3- to 10-GHz frequency bands. The ILRO also allows for duty-cycled coherent mode operation with 2–4-ns phase locking time and binary phase modulation is applied directly on the oscillator. The on-chip digital front end enables duty cycling (DC) of analog front-end modules with a granularity of 2 ns. Implemented in 28-nm CMOS process, this chip is measured to consume 4.9-mW power in nominal mode with IEEE 802.15.4z high pulse repetition frequency (HPRF) compatible data rate of 6.81 Mb/s compliant with major spectrum mask regulations for channels 5 and 9. With DC of the oscillator enabled in the energy-efficient mode, a power consumption of $430~\mu \text{W}$ is achieved for packets compatible with legacy pulse-position-modulated IEEE 802.15.4a standard with a data rate of 27.2 Mb/s. [ABSTRACT FROM AUTHOR]

In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc–dc converter generating fairly large ripples. A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator’s tail current and thus its oscillating amplitude. The parasitic capacitance of the active devices and correspondingly the oscillation frequency are stabilized in turn. A calibration loop is also integrated on-chip to automatically set the optimum replication gain that minimizes the variation of the oscillation amplitude. A 4.9–5.6-GHz oscillator is realized in 40-nm CMOS and occupies 0.23 mm2 while consuming 0.8–1.3 mW across the tuning range (TR). The supply pushing is improved to <1 MHz/V resulting in a low < −49-dBc spur due to 0.5–12-MHz sinusoidal supply ripples as large as 50 mVpp. We experimentally verify the effectiveness of the proposed technique also in face of saw-tooth, multi-tone, and modulated supply ripples. [ABSTRACT FROM AUTHOR]

In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven tool uses a top-down design approach and generates circuits from specification to layout automatically. A hybrid approach is introduced for different circuits of a SAR ADC: fully synthesized control logic; a script-based flow combining equations, library, and template-based design for the digital-to-analog converter; a lookup table approach combined with selective simulation-based fine tuning and template-based layout generation for the sample and hold; library-based comparator design and script-based layout generation. By balancing the automation and manual effort, the circuit design time is reduced from days down to minutes while still being able to maintain ADC performance. The proposed flow generated two ADC prototypes in 40-nm CMOS, an 8-bit 32 MS/s and a 12-bit 1 MS/s SAR ADC, and enabled excellent power efficiency. The two ADCs consume 187 and $16.7~\mu \text{W}$ at 1-V supply voltage, achieving 30.7 and 18.1 fJ/conversion-step, respectively. [ABSTRACT FROM AUTHOR]

A 1.3 nJ/b IEEE 802.11ah TX for IoT applications is presented. A fully-digital polar architecture consisting of an all-digital PLL-based frequency modulator and an AM-retiming $\Delta \Sigma $ switched-capacitor PA (SC-PA) achieves more than $10\times $ power reduction than state-of-the-art OFDM TXs. Several circuit-design techniques such as LSB truncation error feedback are proposed to efficiently pre-process the AM/PM data to improve the TX performance. A design approach of the SC-PA for optimum overall efficiency is introduced. The PLL spur level is reduced to 55 dBc by a switched-capacitor based digital-to-time converter. A dynamic divider is implemented together with a 1.8 GHz oscillator for efficient LO generation. Fabricated in a 40 nm CMOS process, this TX fulfills all the IEEE 802.11ah mandatory-mode PHY requirements with 4.4% EVM and > 4.8 dB spectral mask margin, while consuming 7.1 mW from a 1 V supply when delivering 0 dBm output power. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low power wireless transceiver specialized for but not limited to medical implantable applications. It operates at the 402–405-MHz medical implant communication service band, and also supports the 420–450-MHz industrial, scientific, and medical band. Being IEEE 802.15.6 standard compliant with additional proprietary modes, this highly configurable transceiver achieves date rates from 11 kb/s to 4.5 Mb/s, which covers the requirements of conventional implantable applications. The phase-locked loop-based transmitter architecture is adopted to support various modulation schemes with limited power budget. The zero-IF receiver has programmable gain and bandwidth to accommodate different operation modes. Fabricated in 40-nm CMOS technology with 1-V supply, this transceiver only consumes 1.78 mW for transmission and 1.49 mW for reception. The ultra-low power consumption together with the 15.6-compliant performance in term of modulation accuracy, sensitivity, and interference robustness make this transceiver competent for various implantable applications. [ABSTRACT FROM PUBLISHER]

This paper presents an ultra-low power 2.4 GHz FSK/PSK RX for wireless personal/body area networks. A single-channel phase-tracking RX based on a sliding-IF phase-to-digital conversion (SIF-PDC) loop is proposed to directly demodulate and digitize the frequency/phase-modulated information. The sliding-IF frequency plan reduces the power consumption of the multi-phase LO generation. A phase rotator is adopted in SIF-PDC to guarantee frequency stability, i.e., avoid the frequency pulling by interference or frequency drift. It equivalently transforms the RF signal processing from the I/Q amplitude domain to a digital-phase domain, which saves up to nearly 40% on power consumption and relaxes the digital baseband complexity. A phase-domain linear model of the proposed SIF-PDC is presented to analyze the frequency response. Fabricated in a 90 nm CMOS technology, the presented RX consumes 2.4 mW at 2 Mbps data rate, i.e., 1.2 nJ/b efficiency, and achieves a sensitivity of –92 dBm. [ABSTRACT FROM AUTHOR]