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This article presents a 5-GS/s 6-bit flash analog-to-digital converter (ADC) in a 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The ADC jointly employs partially active second-stage comparison and $2\times $ time-domain latch interpolation (TDI) to reduce power consumption and avoid extensive calibrations. To enhance the conversion speed of the second-stage structure, the stringent timing constraint is resolved by a 25%–75% duty-cycle clock scheme, a 0.5-bit redundancy in the first comparison stage, and an embedded second-stage slice selection logic. The bandwidth requirements of the track-and-hold (T/H) and T/H buffer under the 25%–75% duty-cycle clock are analyzed. An on-chip successive-approximation (SA)-based comparator offset calibration scheme utilizing FDSOI back-gate bias is also developed, providing sufficient calibration range without impairing comparator speed. The measured prototype achieves a signal-to-noise and distortion ratio (SNDR) of 32.8 dB and a spurious-free dynamic range (SFDR) of 41.82 dB at Nyquist frequency while consuming 15.07 mW power, translating into a Walden figure-of-merit (FOM) of 84.5 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

A hierarchical method for total dose effects simulation of large mixed signal circuits using VHDL-AMS is described. Simplified behavioral models (or macro-models) of small sub-circuits replace SPICE-level circuits. The behavioral models describe the electrical circuit behavior and its dependence on the radiation dose. The behavioral models of sub-circuits can be assembled into complex mixed signal circuits. As a result, the computational cost is reduced significantly compared to conventional SPICE-based methods. The VHDL-AMS method also allows bias-dependent total dose degradation to be coupled to the circuit and operational conditions. Simulation accuracy remains sufficient to determine critical performance metrics of the circuit as the circuit performance degrades with dose. [ABSTRACT FROM AUTHOR]