1. Ultralow Capacitance Transient Voltage Suppressor Design.
- Author
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Lo, Kuo-Hsuan, Huang, Chien-Hao, Weng, Wu-Te, Huang, Tsung-Yi, Su, Hung-Der, Gong, Jeng, and Huang, Chih-Fang
- Subjects
VOLTAGE control ,ELECTRIC capacity ,ELECTRIC potential ,ELECTROSTATIC discharges ,COMPLEMENTARY metal oxide semiconductors - Abstract
A novel transient voltage suppressor (TVS) that features ultralow capacitance is proposed. This structure is able to reduce the input capacitance by 21.1%, and is designed to protect against electrostatic discharge (ESD) issues for high-speed ports. The device is also able to withstand IEC 61000-4-2 contact testing at ±14 kV and transmission line pulse (TLP) testing at 20 A. The device is fabricated using a typical planar Bipolar-CMOS-DMOS (BCD) process. By slotting the doping well to decrease the concentration of diodes, a TVS with an ultralow Cj is obtained without the need to add to the process procedures or without damaging the ESD capability. [ABSTRACT FROM PUBLISHER]
- Published
- 2016
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