Search

A continuous-time (CT) ΣΔ modulator for sensing and direct analog-to-digital conversion of nA-range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source-coupled logic cells to efficiently convert subthreshold current to digital code without performing current-to-voltage conversion. As a benefit of this technique, the current-sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low-power and low-voltage current-mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal-oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current-sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current-mode analog-to-digital converter designs and is comparable with the voltage-mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current-mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current-mode output in ultra low-power conditions and is also suitable to perform on-chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

New circuit design techniques for implementing very high-valued resistors are presented, significantly improving power and area efficiency of analog front-end signal processing in ultra-low power biomedical systems. Ranging in value from few hundreds of $$\hbox{M}\Upomega$$ to few hundreds of $$\hbox{G}\Upomega$$, the proposed floating resistors occupy a very small area, and produce accurately tunable characteristics. Using this approach, a low-pass MOSFET-C filter with tunable cutoff frequency ( f = 20 Hz-184 kHz) has been implemented in a conventional 0.18 μm CMOS technology. Occupying 0.045 mm/pole, the power consumption of this filter is 540 pW/Hz/pole with a measured IMFDR of 70 dB. [ABSTRACT FROM AUTHOR]

Abstract: This article presents a new approach for improving the power-delay performance of subthreshold source-couple logic (STSCL) circuits. Using a simple two-phase pipelining technique, it is possible to increase the activity rate of STSCL gates with negligible additional cost, and hence reduce the total system energy consumption per operation. In the proposed pipelined topology, each STSCL gate is followed by a simple cross-coupled differential pair operating as a state keeper with a very low power consumption and small area overhead. Measurement results on a 32-bit pipelined adder chain fabricated with CMOS technology show that the proposed approach can achieve a significant reduction in power-delay product (PDP) down to 5fJ/stage. [Copyright &y& Elsevier]

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 μm CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 Ω resistor with an output voltage swing of VOD = 400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 mm² and the measured output jitter is σrms = 4.5 p5. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load RC time constant. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 pm CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized. [ABSTRACT FROM AUTHOR]

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 µm CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of 0.045 mmµ /channel, with the total aggregate data bit rate of 20 Gb/s. The measured FTOL is ±3.5% and no error was detected for a 231-1 pseudo-random bit stream (PRBS) input data for 30 minutes, meaning that the bit error rate (BER) is smaller than 10-12. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning range and compensated loop gain has been introduced to tune the center frequency of all CDR channels to the desired value. [ABSTRACT FROM AUTHOR]