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A high image rejection 38 GHz demodulator in TSMC 65-nm CMOS process is presented. To achieve better than −40 dBc image rejection ratio (IRR), a low I/Q mismatch 45° LO power splitter of sub-harmonic mixer is proposed. In this design, the 45° LO power splitter is composed of a Wilkinson divider, a series delay line with electrical length of 45° on one side of the divider, and a shunt 90° transmission line on the other side. This configuration is attractive because of its design simplicity and easy fabrication. Compared with the conventional techniques that utilize capacitors and inductors instead of the shunt 90° transmission line, the proposed LO power splitter can alleviate the issue of process variation. The demodulator demonstrates an IRR lower than −40 dBc from 37.5 to 41.5 GHz. In addition, conversion gain is 1.3 ± 0.9 dB from 33 to 41 GHz with 6 dBm LO power. The total direct current power consumption is 78 mW from 1.0 V supply voltage. At the modulation scheme of 4096-QAM, the proposed demodulator demonstrates 1.7% (−35.1 dB) error vector magnitude (EVM), which is very close to the EVM measurement floor 1.6% (−36 dB) of our millimeter-wave signal analyzer. [ABSTRACT FROM AUTHOR]

A multiple-frequency continuous-wave (MFCW) agile radar system has the ability to cope with various physiological conditions of a human subject. Following the mathematic model, a favorable carrier frequency for detection is pursued by analyzing the amplitude and composition of the baseband signal. In Experiment-1, a CMOS dual-band transceiver prototype emulate searching a subject from a distance. The frequencies of the dual-band system are 4.26–4.95 GHz and 17.06–19.79 GHz. During the experiment, the respiratory signal could be detected up to 12 m, and the heartbeat signal up to 6 m. Even with a wooden or a brick barrier in the path, the vital-sign detection remained satisfactory. Later, a concurrent MFCW detection is performed in Experiment-2 for more precise analyses. From the concurrent results, the breathing status can be inferred, and by cross-correlating the results after the ensemble empirical mode decomposition (EEMD) and principal component analysis (PCA), the nonlinear effects of respiratory harmonics or intermodulation tones are reduced, resulting in an accurate heart rate extraction. The receiver front-end and the signal source are manufactured using a 180-nm CMOS process, both packaged on an RO4003C printed-circuit board (PCB). [ABSTRACT FROM AUTHOR]

A 3.5 GHz low insertion loss variation phase shifter has been designed and fabricated on standard 0.18‐μm CMOS process. To achieve over 360° continuously phase tuning range, the phase shifter consists of a switch type phase shifter (STPS) and a reflection type phase shifter (RTPS). The phase‐invertible variable attenuator (PIVA) topology which can provide two states with 180° phase‐shift while maintaining low amplitude imbalance is adopted. The RTPS provides over 189° continuously phase tuning. The experimental results show that the 3.5 GHz phase shifter demonstrates over 360° continuously phase tuning range with low insertion loss variation of 1 dB at 3.5 GHz. The maximum insertion loss is 13.5 dB at 3.5 GHz and the dc consumption is zero. The chip size is 1.08 mm × 0.82 mm. [ABSTRACT FROM AUTHOR]

Abstract: In this letter, a dual‐band class‐E CMOS power amplifier (PA) in 0.18‐μm CMOS process is presented. By using concurrent dual‐band impedance matching network, the proposed dual‐band PA can achieve high efficiency in a compact chip area. This dual‐band class‐E PA demonstrates the power gain ≥ 8.4 dB, Psat ≥ 21.4 dBm with power added efficiency ≥ 31% in a compact chip size of 0.5 mm2. This dual‐band class‐E PA achieves comparable power area density of 284.5 (mW/mm2) with other state‐of‐the‐art class‐E PAs at higher frequency. [ABSTRACT FROM AUTHOR]

A 224-448 MHz low-power fully integrated phase-locked loop (PLL) is designed and implemented in standard 0.18-μm CMOS process. For wide tuning rage and compact circuit size, a differential ring-type voltage-controlled oscillator (VCO) is adopted. The replica bias circuit is added to provide the required voltage for the delay cell of the VCO. For low dc consumption, a high-speed true single phase clock (TSPC) divider is used. The PLL achieves wide operating frequency from 224 to 448 MHz with low dc power consumption of 2.62 mW from 1.8 V voltage supply. The measured phase noises are −98 and −115 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. [ABSTRACT FROM AUTHOR]

ABSTRACT This article presents a wideband phase-locked loop (PLL) front-end, which consists of a dual-core voltage-controlled oscillator (VCO) and a divide-by-four (D4) frequency divider in 90-nm CMOS technology. The switched inductors and varactor banks are used to enhance the tuning range of VCO. The D4 frequency divider is a body-biased injection-locked frequency divider (ILFD) cascoded with source-injection current mode logic (SICML) for wider locking range and lower power consumption. This PLL front-end demonstrates a 30.2% frequency tuning range (FTR) from 23.6 to 32 GHz and a phase noise of −101.22 dBc/Hz at 5.86 GHz with 1 MHz offset frequency. The output power is higher than −15 dBm among the operating bandwidth. The dc power consumption is 40.8 mW at 1.2 V and 1.5 V supply voltages. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:1305-1309, 2017 [ABSTRACT FROM AUTHOR]

ABSTRACT A K-band differential cross-coupled inductance- capacitance (LC) voltage-controlled oscillator (VCO) is implemented in 0.18-μm CMOS process. To accomplish high quality (Q) factor LC-tank at K-band, a slab inductor with high Q is adopted. The VCO can be tuned from 23.1 to 23.38 GHz and the core dc power consumption is 11.33 mW from 1 V power supply. The phase noise is −109.04 dBc/Hz at 1 MHz offset, and the calculated figure of merit (FoM) is −185.79 dBc/Hz. At low supply voltage mode of 0.65 V, the phase noise is −106.015 dBc/Hz at 1 MHz offset and the FoM is −189.76 dBc/Hz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:362-366, 2017 [ABSTRACT FROM AUTHOR]

A 12–32 GHz divide-by-2 (D2) injection-locked frequency divider (ILFD) is presented in this paper. First, the device ratio of the injection mixer and cross-coupled pair is optimized to achieve a wide locking range (LR). Then, the inductive peaking and forward-body-bias techniques are applied to the injection mixer to boost its transconductance and to enhance injection efficiency for further extension of the LR. Finally, the harmonic suppression technique is introduced to reduce the output harmonics. Using the aforementioned approaches, we successfully demonstrate a D2 ILFD implemented in the 90-nm low-power CMOS technology with a maximum LR of 90.9% at an injection power of 0 dBm. Even with the injection power as low as −10 dBm, the proposed ILFD maintains an LR of 32.9%. This ILFD consumes 2.4 mW with a supply voltage of 0.6 V in a chip size of 0.45 mm2. [ABSTRACT FROM PUBLISHER]

ABSTRACT A V-band variable gain amplifier (VGA) with wide gain control range, low phase variation, and low return loss variation is designed and implemented on 90-nm CMOS process. Utilizing a phase compensation capacitor at the common gate transistor and a source degeneration inductor at the common source transistor of the cascode configuration, the VGA achieves gain control range of 15.8 dB with only 6.9° transmission phase variation at 60 GHz via simple control mechanism. The maximum small signal gain is 15.8 dB at 60 GHz. In addition, the input/output return losses are insensitivity at different gain state of the VGA. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1946-1949, 2014 [ABSTRACT FROM AUTHOR]

An E-band high image-rejection sub-harmonic in-phase/quadrature (IQ) modulator for a high-order quadrature amplitude modulation (QAM) signal is designed and implemented on standard 65-nm CMOS technology. To maintain high image-rejection ratio of the IQ modulator over a wide bandwidth for high data-rate application, a load-insensitive analysis and a local oscillator (LO) broadband 45^\circ power splitter are proposed to achieve low amplitude and phase imbalanced structure. In addition, the doubly balanced sub-harmonic Gilbert-cell mixer with the advantages of good LO leakage suppression has been selected in the mixer design. The IQ modulator demonstrates a measured flat conversion gain of 0 \pm 1 dB from 55 to 85 GHz. The image rejection ratio is better than 40 dBc from 64 to 84 GHz. For millimeter-wave communication applications, the IQ modulator is integrated with a four-stage power amplifier to form a direct-conversion transmitter. The measured conversion gain of the transmitter is 33 dB and the measured saturated power is 11 dBm. Via high image rejection and good LO suppression of the modulator, a 1024-QAM modulated signal with a data rate of 500 Mb/s and 1.7% error vector magnitude is successfully demonstrated at 65 GHz. [ABSTRACT FROM PUBLISHER]

An ultra-low-power consumption and ultra-low local oscillator (LO) power double-balanced down-conversion mixer using standard 90-nm CMOS technology is presented in this paper. By employing a weak inversion biasing technique in a source-driven topology, the proposed V-band mixer can operate at microwatt power consumption of 453 \mu\W and has an ultra low LO power of -\6 dBm. In addition, under 1.2-V standard supply voltage, the down-conversion mixer exhibits excellent conversion-gain flatness of \ 5.9\pm\ 1.5~\ dB and the measured LO-to-RF isolation is more than 37 dB from 53 to 70 GHz, and OP1 dB of -\9.2 dBm at RF frequency of 60 GHz. Based on aforementioned results, the presented monolithic microwave integrated circuit can mitigate power-hungry issues while providing reasonable RF performance, which is important for a low-power communication system. [ABSTRACT FROM AUTHOR]

An innovative on-chip 3-D power amplifier (PA) architecture for M-way power-combined CMOS PAs by using the proposed dual-radial symmetric architecture is presented. It provides design freedom of impedance selection of power device in transformer-based millimeter-wave PA design. This idea also makes distinguished breakthrough to the traditional 2-D PA architecture without compromising symmetry and compact size of layout. To demonstrate the feasibility of this idea, a 60-GHz PA is fabricated in 90-nm low-power CMOS process. It is also equipped with multi-mode operation. It achieves an output power of 18.5 dBm and a power-added efficiency of 10.2% with 1.2-V supply voltage. At 6-dB/10-dB power back-off operation, the drain efficiencies of power stage can be enhanced from 5.9%/2.4% to 11.9%/8%, respectively, by enabling the multi-mode operation. [ABSTRACT FROM AUTHOR]

A 57–64-GHz low phase-error 5-bit switch-type phase shifter integrated with a low phase-variation variable gain amplifier (VGA) is implemented through TSMC 90-nm CMOS low-power technology. Using the phase compensation technique, the proposed VGA can provide appropriate gain tuning with almost constant phase characteristics, thus greatly reducing the phase-tuning complexity in a phased-array system. The measured root mean square (rms) phase error of the 5-bit phase shifter is 2^\circ at 62 GHz. The phase shifter has a low group-delay deviation (phase distortion) of +/-8.5 ps and an excellent insertion loss flatness of \pm0.8 dB for a specific phase-shifting state, across 57–64 GHz. For all 32 states, the insertion loss is 14.6 \pm 3 dB, including pad loss at 60 GHz. For the integrated phase shifter and VGA, the VGA can provide 6.2-dB gain tuning range, which is wide enough to cover the loss variation of the phase shifter, with only 1.86^\circ phase variation. The measured rms phase error of the 5-bit phase shifter and VGA is 3.8^\circ at 63 GHz. The insertion loss of all 32 states is 5.4 dB, including pad loss at 60 GHz, and the loss flatness is \pm0.8 dB over 57–64 GHz. To the best of our knowledge, the 5-bit phase shifter presents the best rms phase error at center frequency among the V-band switch-type phase shifter. [ABSTRACT FROM AUTHOR]

A bandwidth-enhanced technique for a Miller divider is presented in this paper. The proposed frequency divider consists of a band-switched Miller divider and digital-assisted circuit to switch the resonator automatically. The proposed frequency divider is implemented in \0.18-\mu\ m CMOS technology and has a measured 57.4% bandwidth from 8.2 to 14.8 GHz at an input power of 0 dBm. The dc consumption is 12 mW. Compared to the previously reported Miller dividers, the proposed circuit achieves the widest fractional bandwidth. [ABSTRACT FROM AUTHOR]

Two \mbi V-band low-noise amplifiers (LNAs) with excellent linearity and noise figure (NF) using 90-nm CMOS technology are demonstrated in this paper, employing parasitic-insensitive linearization topologies, i.e., cascode and common source, for comparative purposes. To improve the linearity without deteriorating the NF, the 54–69-GHz cascode LNA is linearized by the body-biased post-distortion, and the 58–65-GHz common-source LNA is linearized by the distributed derivative superposition. Using these parasitic-insensitive linearization methods at millimeter-wave frequency, the cascode LNA can achieve an IIP{\bf 3} of 11 dBm and an NF of 3.78 dB at 68.5 GHz with a gain of 13.2 dB and 14.4-mW dc power. The common-source LNA has an IIP{\bf 3} of 0 dBm and an NF of 4.1 dB at 64.5 GHz with a gain of 11.3 dB and 10.8-mW dc power. To the best of our knowledge, the proposed cascode LNA has up to 11-dBm IIP{\bf 3} performance and the highest figure-of-merit of 156.2, among all reported V-band LNAs. [ABSTRACT FROM AUTHOR]

A cascoded frequency divider (FD) with division number of 4 and ultra-wide locking range is presented in this paper. The proposed FD consists of a divide-by-2 (D2) injection-locked frequency divider (ILFD) core and a D2 source-injection current mode logic (SICML) divider. After the cascoded integration of ILFD and SICML, the removal of transconductance and buffer stages can lower the dc power consumption and widen the locking range. The proposed FD is implemented in 0.13-\mu\ m CMOS technology and has a 77.3% frequency locking range from 13.5 to 30.5 GHz at injection power of 0 dBm while consuming 7.3-mW dc power. Compared to the previously reported ILFDs, the proposed circuit achieves the widest locking range without employing extra tuning mechanism. [ABSTRACT FROM AUTHOR]

A 53-67 GHz wide locking range injection-locked frequency divider (ILFD) has been designed and fabricated using 0.13-μm CMOS process.By using forward body bias technique, the proposed ILFD demonstrates good performance of the wide locking range while maintaining low DC power consumption. Via a 0 dBm incident signal power, an input locking rage greater than 14 GHz (>23%) is achieved with 4 mW from supply voltage of 0.8 V. If the supply voltage further reduces to 0.6 V, the input locking rage is 6 GHz (10%) while consuming only 1.2 mW. Compared to previous reported works in high-speed CMOS FD, the presented ILFD achieves superior figure of merit (FOM). Without extra voltage control mechanisms to increase the locking range, this FD covers whole 57-64 GHz band is suitable for integration into a 60 GHz WPAN phase-locked loop system. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:1386-1389, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25989 [ABSTRACT FROM AUTHOR]

In this paper, low-voltage evolution and high-speed operation mixer design are presented for millimeter-wave (MMW) CMOS in-phase/quadrature (I/Q) modulator and demodulator. The modified Gilbert-cell mixer architecture, which eliminates the three-level transistors stacking in the conventional Gilbert-cell mixer, can operate at a reduced supply voltage while maintaining reasonable performance. In addition, IF transimpedance amplifier buffer and wideband RF design are introduced to increase the operation speed of the mixer for MMW gigabit wireless transmission link applications. Using a 0.13-\mum CMOS process, the I/Q modulator and demodulator formed with the modified Gilbert-cell mixers are demonstrated at the MMW. Under 1.2-V standard supply voltage, the modulator and demodulator exhibit excellent conversion gain (CG) flatness of -\3.5 \pm \1.5 dB and -\3 \pm \1.5 dB from 41 to 69.5 GHz and 31 to 69 GHz, respectively. For 60-GHz wireless personal area network applications, \pi/4 differential quadrature phase-shift keying, 16 quadrature amplitude modulation, and binary phase-shift keying modulation signal tests are successfully performed through the direct-conversion system. The results show that the presented monolithic microwave integrated circuits can operate at low-voltage and low-power while providing good CG and high data rate, even up to multigigabit. [ABSTRACT FROM AUTHOR]

In this letter, a low-voltage and low-power 3.5-GHz low noise amplifier (LNA) is designed and fabricated using TSMC 0.18-μm MS/RF complementary metal-oxide-semiconductor field effect transistor (CMOS) technology. The complementary current-reused topology is utilized to achieve low dc power consumption while maintaining reasonable gain performance. Consuming 1.38 mW dc power from 0.6 V supply, the LNA achieves a small signal gain of 16.09 dB and a noise figure of 4.702 dB at 3.5 GHz. Compared with previously reported LNA, the MMIC has excellent FOM performance. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:145-147, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26463 [ABSTRACT FROM AUTHOR]