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Continued scaling of Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology is slowing down due to physical limitations, while the static power of CMOS based memory is increasing as the transistors shrink. As an alternative memory technology, the Spin Transfer Torque Magnetic RAM (STT-MRAM) remains limited to low-level, high-capacity caches because of the high write power and still unsatisfactory write access speed. Spin Orbit Torque MRAM (SOT-MRAM), which has been proposed to tackle this issue, still faces some issues including the poor read margin due to low Tunnel Magnetoresistance (TMR) and undesirable use of a magnetic field for deterministic switching. This article proposes a novel 3T2SOT (three Transistors and two SOT magnetic tunnel junctions) based field-free MRAM, which can achieve higher read speed and reliability by adopting a self-referencing scheme, and lower write power benefiting from an advanced switching mechanism. Detailed circuit-level simulation results show that the write latency of the proposed design can be reduced to $0.3~ns$ , and the write power is two orders of magnitude lower than STT-MRAM. Additionally, compared to SRAM, for 8 MB cache memory, the read speed of 3T2SOT MRAM is enhanced by 38.9%. Compared to conventional 2T1SOT MRAM, the read performance is similar and the read error rate is dropped by 96.1% at least. [ABSTRACT FROM AUTHOR]