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A direct conversion transmitter with low noise and low power is presented in this article.A quadrature driver amplifier is used to remove the Inphase-Quadrature crosstalk in a passive mixer operating with 50% duty cycle local oscillator (LO). In the quadrature LO generation, an inductor-less injection-locked frequency divider is utilized to reduce the phase noise contribution with cost of a small current and area. Fabricated in 65 nm CMOS process, a transmitter prototype is designed for wideband code division multiple access (WCDMA) application. Measurement results show that the proposed transmitter achieves 1 dBm maximum output power at 2.53 GHz, 1.7% error vector magnitude (EVM), and −158.5 dBc/Hz output noise at the receiver (RX) band, eliminating the need for the surface acoustic wave (SAW) filter in a traditional transmitter design, with an area of 0.18 mm2 and a total power consumption of 37.8 mW. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1217-1221, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27571 [ABSTRACT FROM AUTHOR]

A fully integrated dual-channel multiband RF receiver is designed and implemented for next-generation global navigation satellite systems (GNSSs) in a 0.18-\mu\ m CMOS process. Its two reconfigurable signal channels can simultaneously process any two types of 2-, 4-, or 20-MHz bandwidth signals mainly located around the RF bands of 1.2 and 1.57 GHz for GPS, Galileo, and BD-2 (aka Compass) systems, while achieving better performance (die area, noise figure, gain dynamic range) than other state-of-the-art GNSS receivers. A digital automatic gain control loop consisting of a variable gain amplifier and nonuniform 4-bit ADC is utilized to improve the receiver's robustness and performance in the presence of interferences. While drawing 25-mA current per channel from a 1.8-V supply, this RF receiver achieves a total noise figure of 2.5 dB/2.7 dB at 1.2/1.57 GHz, an image rejection of 28 dB, a maximum voltage gain of 110 dB, a gain dynamic range of 73 dB, and an input-referred 1-dB compression point of -58 dBm, with an active die area of 2.4 \ mm^2 for single channel. [ABSTRACT FROM PUBLISHER]

A tri-mode RF receiver with all digital automatic gain control (AGC) loop and non-uniform 2-bit analog-to-digital converter (ADC) is designed for the bands of GPS-L1, Galileo-E1 and Compass B1 in 0.18 μm CMOS process. The RF front-end, analog baseband and frequency synthesizer with voltage controlled oscillator (VCO) have been integrated, and there are only few off-chip components including bypass capacitances, matching network and TCXO. For anti-jamming consideration, an all digital AGC loop with relevant variable gain amplifier (VGA) and non-uniform ADC is implemented to suppress interference and avoid saturation of signal chain. While drawing 35 mA current, this receiver achieves a total noise figure of 4 dB and a maximum gain of 105 dB, with a die area of 2.4 × 2.4 mm. [ABSTRACT FROM AUTHOR]

In this article, a 0.5 V X-band low noise amplifier (LNA) composed of two common-source stages is designed and fabricated with 0.18 um CMOS technology.Based on the structure of cascaded common-source stages and forward body bias technology, the supply voltage is reduced. Measurement results show that the circuit can operate at supply voltage of 0.5 V with 8 mA current occupation. The gain is 9.1 dB, noise figure is 5.0 dB, and IIP3 is −8.5 dBm at frequency of 8.9 GHz. The whole performance of the amplifier defined by two kinds of figure-of-merits is compared with some published LNAs. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:17-20, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25641 [ABSTRACT FROM AUTHOR]

This paper presents a sampling PLL (SPLL) using a gain-boosted sampling phase-frequency detector (SPFD) to suppress in-band phase noise. The implementation of the SPFD eliminates the need for a frequency-locked loop (FLL). Additionally, a cycle slipping elimination (CSE) technique is incorporated into the SPFD to enhance the locking speed of the SPLL. The proposed SPFD achieves phase detection gain multiplication by sampling both rising and falling slopes simultaneously, effectively reducing the noise contribution of building blocks with low-pass characteristics without compromising the linear phase detection range. To enhance the reliability of the SPFD, a phase detection gain calibration strategy is proposed, involving a replica capacitor array and a successive approximation algorithm, ensuring a consistent phase detection gain. Moreover, by integrating capacitive coupled noise circulating (CCNC) technique and 2nd harmonic control (F 2) technique, a low noise CCNC–F 2 VCO is introduced to further suppress out-of-band phase noise of the SPLL. Implemented using a 28 nm CMOS process, the SPLL employing the SPFD and CCNC–F 2 VCO achieves a fitted RMS jitter of 61 fs integrated from 10 kHz to 100 MHz at an operating frequency of 4 GHz. The SPLL consumes 20.1 mW, occupies an area of 0.26 mm2 and achieves a jitter figure-of-merit (FoM) of −251.3 dB. [ABSTRACT FROM AUTHOR]

A fully integrated ultra-wideband fractional- N frequency synthesizer is presented in this paper. Ultra-wideband quadrature signals can be generated by an octave-wide fractional- N phase-locked loop (PLL) and an ultra-wideband local oscillator (LO) signal generator. An optimized dual-core voltage-controlled oscillator (VCO) is employed to maintain relatively constant loop parameters in the octave-wide operating range, while a negative-capacitance VCO (NC–VCO) is proposed to solve the frequency gap problem and enhance the design freedom of the wideband VCO. Moreover, a wide-range programmable multi-modulus divider (PMMD) with seamless switching and fractional division resolution is proposed for error-free division operation and quantization noise compensation in the fractional- N mode, respectively. Power-efficient design is mainly achieved by the presented hybrid LO generator with optimized divider topologies for different frequency ranges. Fabricated in a 55 nm CMOS process, 0.023–12 GHz continuous quadrature LO signals can be generated by the proposed frequency synthesizer which occupies an active area of 0.55 mm2 and consumes 75–104 mW from a 1.2 V supply. The measured phase noise is −108.1 dBc/Hz at 1 MHz offset from a 12 GHz carrier, and the I/Q phase error is less than 2.7° with FOM T of −251.8 dB. [ABSTRACT FROM AUTHOR]

A low power receiver is designed and implemented for 2.4 GHz Industrial-Scientific-Medical (ISM) band in a 40 nm CMOS process. To obtain good noise and linearity performance at low cost, a current-reused low power inductor-less balun low noise amplifier (LNA) structure is proposed without use of monolithic spiral inductors or transformers. The receiver adopts a zero-IF architecture and current mode mixing operation which avoid need of large voltage headroom for the radio frequency (RF) voltage swing under strong interferers. A third order active-RC low pass filter (LPF) with RC calibration and DC offset cancelation (DCOC) blocks are carefully designed. Current reusing technique and timing optimized asynchronous SAR logic are adopted in LNA and ADC design respectively, featuring high-power efficiency. The total receiver chain achieves maximum conversion gain of 80.32 dB, noise figure (NF) of 6.27 dB and input referred third-order intercept point (IIP3) of −0.6 dBm with 32.8 mW power consumption. [ABSTRACT FROM AUTHOR]

A fully integrated high efficiency switched-capacitor (SC) DC-DC converter with pulse frequency modulation (PFM) control is presented. The small signal model of the multiphase-interleaving SC converter is given and it is verified through the simulation and the measurement results. For high efficiency, this design set the dominant pole at the output of the error amplifier (EA) and the 14-phase interleaving topology can push the non-dominant pole away from the Unit Gain Frequency (UGF) for the loop stability. By combining the flying-well and the deep n-well (DNW) isolation techniques, the proposed high-density MOS capacitor can reduce both the parasitic loss and the charge sharing loss of the converter. The conversion ratio of the converter is 2:1 under 3.3V power supply. This SC DC-DC converter is fabricated in the 40 nm CMOS process. It obtains the peak efficiency of 86.2% and the output power-density of 226 mW/mm2. It maintains the efficiency above 80% from 8 mA to 50 mA load condition. [ABSTRACT FROM AUTHOR]