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Summary: We propose a novel CMOS differential voltage‐controlled equivalent active resistor based on a modified common‐source cross‐coupled pair. The equivalent resistance exhibited by the circuit can be tuned to be either positive or negative through the tail current, which is controlled by a bias voltage. The complete cell comprises four transistors, two resistors in addition to the bias voltage, and tail current source. Application to the design of oscillators is demonstrated by theoretical analysis, circuit simulations, and verified experimentally through measurements on prototypes implemented using discrete transistors. In this work, we propose a novel tunable negative or positive differential resistance implemented using four transistors, which offers an advantage over the conventional cross‐coupled differential pair. The advantage being that the equivalent resistance exhibited by the circuit can be tuned to be either negative or positive through a tail current as well as via a bias voltage. Its linearity and range of operation are examined, and applications to oscillators are demonstrated through simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper reports the analyses of the inductive degeneration, noise filter, and optimum current density techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. The design of the circuit topology is carried out in 28 nm bulk CMOS technology in a range of common conditions adopted also for a previous study on the Colpitts topology, so complementing the previous study on Colpitts topology and allowing a direct comparison between the Hartley and Colpitts topologies. The theoretical analyses of the three techniques are carried out and verified by means of circuit simulations. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. Moreover, the results obtained for the optimum bias current density technique applied to a Hartley oscillator circuit topology incorporating either inductive degeneration or noise filter provide the demonstration of the existence of an optimum bias current density for minimum phase noise. Moreover, we will go beyond this important result, by investigating for the first time the relationship with the optimum current density for transistor minimum noise figure and other general results reported in the literature. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 16 dB at a 1 MHz frequency offset for an oscillation frequency of 10 GHz, with respect to the traditional Hartley topology. Lastly, we report a comparison under common conditions between Colpitts and Hartley topologies implementing the aforementioned techniques, which could, from a designer perspective, be useful to acquiring a few key insights about the circuit design opportunities and focus the design efforts toward specific directions for performance optimizations. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper presents two 4-bit (16-phase) mm-wave vector modulator phase shifters exploiting a novel in-phase and quadrature signal generator that consists of a single-input double-output cascode amplifier incorporating a lumped-element coupled-line quadrature coupler. The two circuit implementations have been designed and fabricated in a 28 nm fully depleted silicon-on-insulator CMOS. The first (PS1) achieves a higher gain and the second (PS2) has a more compact area (reduced to about 50%). Each consumes 18 mA from a 1.2 V supply. PS1 exhibits an average gain of 2.3 dB at 87.4 GHz and B3\text {dB} from 78.8 to 92.8 GHz; rms gain error of 1.68 dB at 87.4 GHz and <2 dB in the B3\text {dB} ; rms phase error of 9.4° at 87.4 GHz and <11.9° in B3\text {dB} ; S11 <-10.5 dB in B3\text {dB} ; average P1\text {dB} of −7 dBm; and average noise figure (NF) equal to 10.8 dB at 87 GHz. PS2 exhibits an average gain of 0.83 dB at 89.2 GHz and B3\text {dB} from 80.2 to 96.8 GHz; rms gain error of 1.46 dB at 89.2 GHz and <2 dB in B3\text {dB} ; rms phase error of 11.2° at 89.2 GHz and <11.9° in B3\text {dB} ; S11 <-11.5 dB in B3\text {dB} ; average P1\text {dB} of −6 dBm; and average NF of 11.9 dB at 89 GHz. [ABSTRACT FROM AUTHOR]

This paper reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10, and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano-scale CMOS LC oscillators. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

The potential of active inductors (AIs) has been often reduced by lack of accurate design methodologies and limitations due to the inherent noise sources. This paper deals with these two open issues for a high-frequency CMOS AI characterized by high-quality factor, low-power consumption, and low noise. First, it reports an effective design methodology for the implementation of high-frequency CMOS AIs with a high-quality factor. In particular, it shows how, through an advanced small-signal circuit model, to carry out an accurate and reliable design at high frequency (over 10 GHz) in modern nanoscale CMOS process. The design methodology is validated through cases of study at 13 GHz implemented in a standard 90-nm CMOS process and characterized experimentally. The results show that the AI exhibits an equivalent inductance close to 3.2 nH with an associated quality factor close to 200. After, it reports a noise analysis. It shows that the AI exhibits a very low level of noise, enabling its application to the implementation of high-quality factor low-noise LC tank in high-frequency building blocks of radio frequency front-ends. The results show that the AI exhibits a noise power spectral density lower than −150 dBm/Hz. [ABSTRACT FROM AUTHOR]

Comparative Phase Noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong differential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1 GHz to 100 GHz, are carried out in order to identify their relative performance. The impulse sensitivity function (ISF) is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of five distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the ISF show the impact of flicker noise contribution as the major effect leading to phase noise degradation in nanoscale CMOS LC oscillators. [ABSTRACT FROM AUTHOR]

Passive radiometry is a health-safe alternative to other imaging techniques conceived to be used on human beings for security screening or medical imaging applications. In this work we address a study on the feasibility of W-band passive radiometers in nano-scale CMOS technology for imaging applications. In particular, this study takes into account some of the most relevant aspects regarding the system-on-a-chip implementation, from system to circuit and technology limitations, with emphasis on the impact of the non-idealities of the detector on the overall system performances. Excluding the hardware differences between the investigated receiver architectures and their substantial implications, especially in case of array systems, the investigation shows how there is no a clear evidence to identify a priori the best performance receiver architecture, but it depends on the circuits, as well as operating frequency and technology. [ABSTRACT FROM AUTHOR]

This paper reports the latest advances on millimeter-wave CMOS voltage-controlled oscillators (VCOs). Current state-of-the-art implementations are reviewed, and their performances are compared in terms of phase noise and figure of merit. Low power and low phase noise LC-VCO and ring oscillator designs are analyzed and discussed. Design and performance trends over the last decade are provided and discussed. The paper shows how for the higher range of millimeter-waves (>60GHz) the performances of ring oscillators become comparable with those of LC-VCOs. [ABSTRACT FROM AUTHOR]