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A description of a highly efficient CMOS process technique of suppressing the transmission of high-frequency noise is presented. Through the experiments conducted it is noticed that the heavily doped n+-pocket structures exhibited the best performance in noise suppression at high frequencies.

An investigation into the characteristics of the dark signals in the CMOS active pixel sensor (APS) with test structures fabricated using the deep-submicron CMOS technology was undertaken. The results showed that the periphery of the photodiode (PD) is the dominant source of dark currents in test structures that is very sensitive to the distance between the sidewall of the shallow trench isolation and the n-type region of the PD.

Using rapid vapor-phase doping (RVD) for pMOSFETs and solid-phase diffusion (SPD) for nMOSFETs, an advanced CMOS process is developed. The effect of the source/drain (S/D) extension structure on the device performance is also investigated.

Si/SiGe resonant interband diodes (RITDs) employing delta-doping spikes that demonstrate negative differential resistance (NDR) at room temperature are presented. Efforts have focused on improving the tunnel diode peak-to-valley current ratio (PVCR) figure-of-merit and addressing issues of manufacturability and CMOS integration.

The CMOS imaging for automotive applications are described. CMOS imaging fulfills the requirements posed by automotive vision applications.

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512 * 512 resolution) CMOS active pixel sensor (APS) is described. A comparison is conducted between a column-parallel active pixel sensor (APS) and a digital pixel sensor (DPS).

A new front-end for photodiode-based CMOS imagers is described. The design and operation of a flushed-reset pixel is discussed

A novel architecture for CMOS active pixel image sensors (APSs) eliminates the vertically striped fixed pattern noise (FPN). There is a proposal for a buried-photodiode device with the transversal-readout architecture.

The development of a micropower 176*144 CMOS active pixel image sensor is described. A low-power sensor design methodology is applied throughout the design process from system-level to process-level to obtain the design goals.

The design and fabrication of a 512*512 CMOS active pixel sensor (APS) in a standard 0.5-mu m technology is described. The increase of the dark current is the most pronounced radiation effect.

The top-down design of an active pixel sensor (APS) circuit using an analytical model of its architecture is described. The model assists in the comparison of the performances of bulk versus silicon-on-insulator (SOI) CMOS processes and devices on the designs and performance of several 50-frames/s imagers in 2-mu m and 0.25-mu m CMOS with different pixels array sizes.D

The development of an ultralow dark-signal and high-sensitivity pixel for an embedded active-pixel CMOS image sensor is described. A combined photogate/photodiode photon-sensing device with a novel operation scheme is developed to achieve in-pixel dark-current cancellation.

The leakage current mechanisms in diodes to model the dark current of various pixel architecture for active pixel CMOS image sensors are described. The various contributions to the leakage current are determined by the study of dedicated test structure made in 0.35-mu m CMOS.

The development of a stacked CMOS-active pixel sensor (APS) with a newly devised pixel structure for charged particle detection is described. Nondestructive readout correlated double sampling (CDS) with the correlated double sampling (CDS) interval of 21 seconds assisted in achieving the total read noise floor of 0.1 mV(sub rms) at the pixel electrode.

A new signal readout method is introduced for ultrahigh-sensitivity CMOS image sensor. This method uses a charge-transfer circuit to obtain high signal-to-noise ratio features.

An NMOS-only pixel with a global shutter and subthreshold operation of the NMOS sample-and-hold transistor is described. This approach increases the optical responsivity by a factor of five to 9 nu V/photon.

The development of a low-leakage current and low-operating-voltage buried-photodiode structure of CMOS image sensors is described. A modified fabrication process and an additional shallow p+ layer structure were adopted by the new structure

A CMOS image sensor with a vertically integrated double-junction photodiode structure is described. The imaging performance of an integrated two-filter color sensor is discussed.

The three-dimensional (3-D) device simulator SPECTRA and a 3-D optical simulator TOCCATA are used for analyzing the optical and electrical characteristics of CMOS image sensors and crosstalk characteristics. Ray-tracing and current calculation is used for the individual analysis of the optical and electronic crosstalk.

The development of a semi-analytical model for photoresponse estimation of a photodiode-based CMOS active pixel sensor (APS) is described. The model is suitable for implementation in photoresponse simulation of CMOS photodiode arrays due to its simplicity and accuracy.

The results of crosstalk investigations and microlens (mu-lens) scan experiments in a color CMOS image sensor with active pixel structure are described. The spectral characteristics measured at different relative apertures (f-number) are discussed.

Active devices under CMOS I/O pads in a 130 nm full eight-level copper metal complementary metal-oxide-semiconductor process are investigated. The active devices under CMOS I/O pads are found independent of bonding pad metal level structures.

The feasibility of higher performance operation is described with the fabrication of the 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide. The reduction of gate current Ig and the prevention of boron penetration in the pFET is possible with the optimization of nitrogen concentration in gate oxynitride.

Source/drain (S/D) engineering using laser annealing in combination with pre-amorphization implantation (PAI) is implemented to the device integration for sub-100-nm CMOS on silicon-on-insulator (SOI) substrate. Pre-amorphization implantation (PAI) controls the ultrashallow junction depth precisely and reduces laser energy fluence required for impurity activation.

The effect of ion implantation for the channel impurity on gate dielectric characteristics, and propose a high-quality and highly thickness-controllable 1.5 nm SiON gate dielectric formation without recoiled-oxygen. It is important to control the film thickness strictly to achieve a low leakage and highly reliable gate-SiON.

Studies conducted on band-to-band tunneling in ion-implanted P/N junction diodes with profiles parameter of future and present silicon complimentary metal oxide-silicon- (CMOS) field effect transistors are described. The results predicting drain to substrate currents and body currents in CMOS transistors are presented.