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This paper proposes an area-efficient fixed-point architecture for the computation of the discrete cosine transform (DCT) of multiple sizes in high efficiency video coding (HEVC). This result is obtained by comparing different DCT factorizations in order to find the most suitable one for implementation in the HEVC encoder. The recursive structure of fast algorithms, which decompose the $N$ -point DCT by means of two $N/2$ -point DCTs, is exploited to execute computations of small-size DCTs in parallel, thus maximizing the hardware re-usability while maintaining a constant throughput. The simulation results prove that the proposed solution features reduced rate-distortion loss es, with relevant complexity saving compared with the state-of-the-art implementations. Finally, the proposed architecture is exploited to design two families of architectures for the 2D-DCT, namely, folded and full-parallel. [ABSTRACT FROM AUTHOR]

Motivated by the importance of hardware implementation in practical turbo decoders, a simplified, yet effective, n-input \max^\ast approximation algorithm is proposed with the aim being its efficient implementation for very low-complexity turbo decoder hardware architectures. The simplification is obtained using an appropriate digital circuit for finding the first two maximum values in a set of n data that embeds the computation of a correction term. Various implementation results show that the proposed architecture is simpler by 30%, on average, than the constant logarithmic-maximum a posteriori (Log-MAP) one, in terms of chip area with the same delay. This comes at the expense of very small performance degradation, in the order of 0.1 dB for up to moderate bit error rates, e.g., 10^-5, assuming binary turbo codes. However, when applying scaling to the extrinsic information, the proposed algorithm achieves almost identical Log-MAP turbo code performance for both binary and double-binary turbo codes, without increasing noticeably the implementation complexity. [ABSTRACT FROM PUBLISHER]

In this paper, we deal with practical implementation issues of the \max^ \ast operation in generalized form used for decoding of both turbo and low-density-parity-check (LDPC) codes. In particular, first, a unified framework for the so-called generalized \max^\ast operation is established, which includes most of the previously published algorithms already known for turbo decoding. Next, the hardware architectures used for the practical implementation of the generalized \max^\ast operation, which is derived from this novel framework, are revealed for the first time and further analyzed, in terms of hardware complexity reduction. It is also shown how this generalized \max^\ast operation can be adopted in LDPC decoding, achieving essentially optimal bit error rate performance with small computational complexity against other algorithms in joint turbo–LDPC architectures. This solution is useful in applications where joint decoding architectures are deployed to decode both turbo and LDPC codes. An important example of such application is in software radio receivers of 4G wireless communication systems, such as those proposed in conjunction with the WiMAX standard. [ABSTRACT FROM PUBLISHER]

With reference to a recently published letter, the purpose of our contribution is two-fold. Firstly, to point out that, what is referred to as a new approximation function MinC (see Eqs. (5)–(8) of Park, 2015) has been previously published (see Eq. (12) of Papaharalabos et al., 2009). Secondly, we present additional related published works of ours, which have further investigated the subject of bitwise log-likelihood ratio (LLR) simplification in soft-output decoding, but have not been mentioned in Park, 2015. [ABSTRACT FROM PUBLISHER]