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In VLSI layout design by the building block approach, a hierarchical floorplanning method is proposed in which the floorplan and global routing are determined simultaneously to realize low-congestion switchboxes. In this method, overlap resolution, which pre- serves relative position and minimizes the obtained chip area, is needed to prevent the increase in the wire length of each net. In this paper, a fundamental study of this overlap resolution Is made, and the following are described. (1) The formulation of the overlap resolution problem RI is given. In the formulation, (a) preservation of relative position among blocks, and (b) the minimization of obtained chip area are considered; (2) the computational complexity of the problem is analyzed, and then NP-completeness of the problem RI is proved; and (3) a polynomial heuristic algorithm R for the problem RI is given. In addition, the result of simulation experiments to verify the efficiency of the heuristic algorithm R is also described. [ABSTRACT FROM AUTHOR]

One of the interesting issues in the management of large computer networks is to partition the network into clusters and then to perform the management for each cluster. This paper presents a basic discussion on the initial clustering problem for a given network. The initial clustering problem C is defined as follows. Given a graphic representation G(V,E), V-n of a network and a set of nodes G-(c)1≤ r ≤ m) &epsive; 1, the graph G is to be partitioned into m connected subgraphs Gi = (Vi, Ei) (1≦i≦m) of G satisfying the following conditions: &o1; V, O C= (c), &o2; V, ≦K (a positive integer); and &o3; the distance between v&epsive; V, and Cx&epsive; C is minimum when x = i. The following results were obtained for the time complexity of the problem C: (1) the initial clustering problem C is in general NP-hard; and (2) the sub-problem obtained by deleting the condition &o2; can be solved in O(n⊃). [ABSTRACT FROM AUTHOR]