Author: "Janidarmian, Majid" / Topic: computer architecture - Searchworks@Jio Institute Digital Library Search Results

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Start Over Author "Janidarmian, Majid" Topic computer architecture

Author: Janidarmian, Majid, Tinati, Melika, Khademzadeh, Ahmad, Ghavibazou, Maryam, and Fekr, Atena Roshan
Subjects: *FAULT tolerance (Engineering), *SYSTEMS design, *RELIABILITY in engineering, *COMPUTER architecture, *DATA transmission systems
Abstract: In this paper a fast and efficient spare switch selection algorithm is presented in a reliable NoC architecture based on specific application mapped onto mesh topology called FERNA. Based on ring concept used in FERNA, this algorithm achieves best results equivalent to exhaustive algorithm with much less run time improving two parameters. Inputs of FERNA algorithm for response time of the system and extra communication cost minimization are derived from simulation of high transaction level using SystemC TLM and mathematical formulation, respectively. The results demonstrate that improvement of above mentioned parameters lead to advance whole system reliability that is analytically calculated. Mapping algorithm has been also investigated as an effective issue on extra bandwidth requirement and system reliability. [ABSTRACT FROM AUTHOR]
Published: 2010
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Author: Koupaei, Fathollah Karimi, Khademzadeh, Ahmad, and Janidarmian, Majid
Subjects: NETWORKS on a chip, COMPUTER algorithms, FAULT-tolerant computing, COMPUTER architecture, MATHEMATICAL mappings, INTEGRATED circuits, NETWORK routers
Abstract: Defect in manufacturing of integrated circuits is almost inevitable, and fast scaling in technology has caused the components of a Network-on-Chip (NoC) to be more susceptible to faults. Therefore, it is crucial to sustain chip production yield and reliable operation in the presence of defects. A fault-tolerant application-specific NoC should be able to detect a fault and recover the system to correctly operate the mapped application. In this paper, a fault-tolerant NoC architecture designed in VHDL and synthesized using Xilinx ISE is presented which not only is able to recover from single permanent router failure, but also improves the average response time of the system in the different traffic loads. As hardware overhead is a major issue while considering fault tolerance, a new component, called Link Interface (LI) is also developed to reduce cost overhead. The Video Object Plan Decoder (VOPD) core graph is used as a real application in this study. [ABSTRACT FROM AUTHOR]
Published: 2012

Author: Tinati, Melika, Khademzadeh, Ahmad, Afzali-Kusha, Ali, and Janidarmian, Majid
Subjects: *MESH networks, *COMPUTER architecture, *FAULT tolerance (Engineering), *SYSTEMS on a chip, *VERY large scale circuit integration, *SWITCHING theory, *RELIABILITY in engineering, *EXPERIMENTAL design
Abstract: Abstract: As the integration of transistors on today’s embedded systems scales, so does the shrinking size of chips, thus making the on-chip communication a challenging issue on the VLSI designs. However, network on chips have emerged as a promising technology to tackle the on-chip communication constraints. Likewise, the reliability issues have become the salient problem, since regarding to the inaccessible failures of on-chip elements, there must be some levels of embedded fault tolerance techniques. In this paper, an innovated technique is revealed providing fault tolerance in the on-chip networks over single and multiple permanent switch failures. The experimental results achieved by the system simulation in SystemC TLM environment are validated with the mathematical analysis modeled for system reliability that we extend in this paper, which demonstrate the extensive reliability enhancement of this paradigm. Along with the system improvement, silicon area overhead is calculated utilizing VHDL low level simulation and Orion synthesis. [Copyright &y& Elsevier]
Published: 2012
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