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This brief presents the implementation and evaluation of an 8-bit adaptable processor core to be part of the power-throughput-area efficient multimedia oriented reconfigurable architecture reconfigurable array. The design of the processor core was custom implemented in IBM's 90 nm CMOS technology and occupies 0.115 mm^2 silicon area with approximately 70% area utilized by core circuits. The processor shows a peak throughput performance of 75 MOPS/mW. Benchmarking results show estimated throughputs of 9.5, 21.36, 39.78, 170.88, and 4.54 MSamples/s for variants of 2-D discrete cosine transform (DCT), 4\,\times\,4 H.264 integer transform, and 2-D discrete wavelet transform, respectively. Our analysis shows that the proposed design provides approximately 4–8 times higher throughput for 2-D DCT when compared against popular architectures. [ABSTRACT FROM PUBLISHER]

Network on-Chips (NoC) have emerged as an attractive communication architecture to address the increasing demand for communication in performance-sensitive applications. Employing differentiated services is a widely used approach to support QoS (Quality of Service) by relatively prioritizing traffic in the networks employing connection-less communication mechanisms. In this paper we present an analytical evaluation of the average message latency for wormhole-routed interconnect architectures exploiting a traffic prioritization mechanism to achieve differentiated services-based QoS. To verify the validity of the model we apply the method to the Spidergon NoC and compare the model against the results obtained from a discrete-event simulator developed using OMNET++. [ABSTRACT FROM AUTHOR]