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We present an Rapid Single Flux Quantum (RSFQ) based high voltage driver (HVD) developed for the first amplification stage of a hybrid semiconductor-superconductor memory interface for the RSFQ digital signal processor. Implementation of the driver allows to eliminate the impedance mismatch between RSFQ and standard 50 Omega input of semiconductor electronics and increases the signal-to-noise ratio to reach reliable signal transmission with sufficiently low bit error rate. The driver design is based on the serial stack of 8 SQUIDs with specially configured ground-cuts that form a quasi-coplanar line with 50 Omega impedance. The impedance of the driver has been extracted using 3D EM simulators that accurately take into account multilayer structure and capacitance to the ground. The circuit has been designed for the Hypres 4.5 kA/cm2 process. The driver was simulated numerically in PSCAN. The driver can produce output signal at 1 Gbit/s speed and 2.4 mV signal level that is enough to be sensed by low-noise amplifier on the further amplification stage.

We report an RSFQ digital signal processor design based on hybrid RSFQ-CMOS memory suitable for a general matrix-on-matrix multiplication algorithm. The DSP consists of an RSFQ multiply-accumulate unit, memory caches and synchronization block, partitioned into multiple chips, and a large CMOS memory. The parameters of the RSFQ DSP are a 10times10 bits multiplication with rounding to 14 bits, an 18-bit accumulator length and a 3.7 Kb memory cache. The maximum simulated clock frequency is equal to 24 GHz for HYPRES 4.5 kA/cm2 process and optimum communication bandwidth with the CMOS memory is 2 Gbps. The simplified version of the RSFQ DSP consisting of a 4times4 MAC with rounding to 5 bits and 17times6 memory caches has been designed for HYPRES 4.5 kA/cm2 process.

The Multiply-Accumulate Unit (MAC) is a central component of a Successive Interference Canceller, an advanced receiver for W-CDMA base stations. A 4*4 two's complement fixed point RSFQ MAC with rounding to 5 bits has been simulated using VHDL and maximum performance is equal to 24 GMACS (giga multiple-accumulates per second). The clock distribution network has been re-designed from a linear ripple to a binary tree network in order to eliminate data dependence of the clock propagation speed and reduce number of Josephson junctions in clock lines. The 4*4 bits MAC has been designed for the HYPRES 4.5 kA/cm^2 process and its components have been experimentally tested at low frequency: the 5 bit combiner, using an exhaustive test pattern, had margins on DC bias voltage of +-18% and the 4*4 parallel multiplier had margins equal to +-2%.

This paper presents results of optimization of Multi-Chip-Module (MCM) contact pads and driver circuitry for gigabit chip-to-chip communication. Optimization has been done using 3D Electromagnetic (EM) simulations of flip-chip contacts and time domain simulations of drivers and receivers. A single optimized flip-chip contact has signal refection of less than -20 dB for up to 503 GHz bandwidth. The MCM data link with optimized SFQ driver, receivers and two MCM contact has operational margins on global bias current of +-30% at 30 Gbit/s speed and can operate at maximum 113 Gbit/s of operational speed. High bandwidth transmission requires realization of an advanced flip-chip process with small dimension of contact pads (less 30 micro meter) and small hight of bumps in the order of 2 micro meter. Current processes with about 7 micro meter hight of the bumps requires application of Double Flux Quantum (DFQ) driver. The data link with DFQ driver was also simulated. It has operational margins on global bias current of +-30% at 30 Gbit/s, however the maximum speed of operation is 61 Gbit/s. Several test structures have been designed for measurements signal re°ection, bit error rate (BER) and operational margins of the data link.

RSFQ high performance digital signal processor capable to perform up to 13 13-bit fixed-point GMACS has been designed for use in successive interference canceller in W-CDMA wireless systems. The performance of the processor has been verified by numerical simulations and VHDL simulation using accurate modeling of the RSFQ gates. Components of the processor, 4 /spl times/ 4 and 5 /spl times/ 5 parallel multipliers, 4 /spl times/ 5, 20 /spl times/ 5 and 4 /spl times/ 15 parallel shift registers have been designed and experimentally tested.

This paper presents timing models for RSFQ cells, based on conventional finite-state machines description. Models have been integrated, validated and verified in physical simulations and are suitable for VHDL design. A complete design flow from physical simulation to VHDL simulation, delays optimization, layouting and back-annotation is presented. The correctness of the timing models has been verified in an experiment with 4 /spl times/ 15 shift register.

A set of standard rapid-single-flux-quantum logic cells has been established in order to build blocks for complex high-speed superconducting digital applications. Special emphasis has been put on the implementation with Nb and NbN technologies as well as with high-Tc superconductors. The influence of the different technological parameters on the projected performance of some basic cells is presented along with a comparative study of their margins of operation. In particular, the performance of a D-flip-flop has been studied as a function of frequency of operation for the different technologies.

In this paper we study the problem of implementing a successive interference canceller (SIC) for a WCDMA system in fixed-point electronics. Typically, fixed-point implementation is based on an iterative design of simulations and experience, resulting in a time-consuming and inefficient process. From the experience of a conventional design with simulations, we make a model of the fixed-point SIC. The advantage with this model is that it can be analyzed and hence be used to predict the performance of a fixed-point implementation with given precision. Simulations indicate that the analysis agrees well for moderate system load and especially for the high precision case. which is the case of most interest. Hence, it much simplifies the design procedure of fixed-point implementation of SIC.