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The Internet architecture works well for a wide variety of communication scenarios. However, its flexibility is limited because it was initially designed to provide communication links between a few static nodes in a homogeneous network and did not attempt to solve the challenges of today’s dynamic network environments. Although the Internet has evolved to a global system of interconnected computer networks, which links together billions of heterogeneous compute nodes, its static architecture remained more or less the same. Nowadays the diversity in networked devices, communication requirements, and network conditions vary heavily, which makes it difficult for a static set of protocols to provide the required functionality. Therefore, we propose a self-aware network architecture in which protocol stacks can be built dynamically. Those protocol stacks can be optimized continuously during communication according to the current requirements. For this network architecture we propose an FPGA-based execution environment called EmbedNet that allows for a dynamic mapping of network protocols to either hardware or software. We show that our architecture can reduce the communication overhead significantly by adapting the protocol stack and that the dynamic hardware/software mapping of protocols considerably reduces the CPU load introduced by packet processing., International Journal of Reconfigurable Computing, 2014, ISSN:1687-7195, ISSN:1687-7209

The ReconOS operating system for reconfigurable computing offers a unified multithreaded programming model and OS services for threads executing in software and threads mapped to reconfigurable hardware. The OS interface lets hardware threads interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard OS environment, ReconOS allows for rapid design-space exploration, supports a structured application development process, and improves the portability of applications between different reconfigurable computing systems.

The objective of autonomic networking is to enable the autonomous formation and parametrization of nodes and networks by letting protocols sense and adapt to the networking environment at run time. Besides its dynamic aspects, a core requirement of autonomic networking is to define a structured framework and execution environment that enables algorithms to operate in a continously changing environment. This paper presents the major design principles of the Autonomic Network Architecture (ANA) and reports on a first implementation. The guiding principle of ANA is to strive for flexibility and genericity at all levels of the architecture. In our approach we explicitly avoid to impose a "one-size-fits-all" architecture (where communication protocols and paradigms are fixed by the architecture). To this end, ANA introduces generic abstractions, for example "information dispatch points" instead of addressable endpoints, as well as communication primitives that support network heterogeneity, adaptability, and evolution. These core abstractions allow for the coexistance of multiple and diverse networking styles and protocols. With the public release of the ANA prototype, we aim at federating autonomics related networking projects, enabling different actors to share, compare, and build upon each other?s work. The ANA runtime can host clean slate network designs as well as legacy Internet technology and serves as a platform for demonstrating autonomic communication principles.

Preemptive hardware multitasking is not supported in most reconfigurable systems-on-chip (rSoCs), which severely limits the scope of hardware scheduling techniques on these platforms. While modern field-programmable gate arrays (FPGAs) support dynamic partial reconfiguration of any region at any time, most hardware tasks cannot be preempted at arbitrary points in time, because context saving and restoring is not supported out of the box by the vendors. Although hardware task preemption techniques have been proposed in the past, they cannot be found in today’s rSoCs. In this paper we therefore propose a novel methodology for preemptive hardware multitasking that does not require any changes at the task level and show that our approach can be seamlessly integrated to an established execution environment for rSoCs, called ReconOS. Our experimental results show that we can successfully capture and restore the states of all flip-flops and block RAMs in a reconfigurable region on a Xilinx Virtex-6 FPGA at arbitrary points in time. Context capturing/restoring can be performed at a bandwidth of 22-28 MB/s, which allows for context switches in the order of milliseconds.

The term Internet of Things is often used to talk about the trend of embedding microprocessors in everyday devices and connecting them to the Internet. The Internet of Things poses challenging communication requirements since the participating devices are heterogeneous, resource-constrained and operate in an ever changing environment. To cope with those requirements, academic research projects have proposed novel network architectures, such as the Dynamic Protocol Stack (DPS) architecture. In this paper, we use smart camera networks as an example of the Internet of Things and evaluate the DPS architecture in this scenario. Our smart camera nodes are implemented as an FPGA-based system-on-chip architecture that uses the DPS architecture for the network communication. We evaluate our smart camera nodes in two case studies. In the first case study, we demonstrate that our proposed smart camera network can track a single object over the field of view of several camera nodes. In the second case study, we show that an adaptive hardware/software mapping of the network functionality can save about 22% of the FPGA resources as compared to a static mapping. The hardware/software mapping can be adapted at a processing delay of a single video frame.

Modern compute systems continue to evolve towards increasingly complex, heterogeneous and distributed architectures. At the same time, functionality and performance are no longer the only aspects when developing applications for such systems, and additional concerns such as flexibility, power efficiency, resource usage, reliability and cost are becoming increasingly important. This does not only raise the question of how to efficiently develop applications for such systems, but also how to cope with dynamic changes in the application behaviour or the system environment. The EPiCS Project aims to address these aspects through exploring self-awareness and self-expression. Self-awareness allows systems and applications to gather and maintain information about their current state and environment, and reason about their behaviour. Self-expression enables systems to adapt their behaviour autonomously to changing conditions. Innovations in EPiCS are based on systematic integration of research in concepts and foundations, customisable hardware/software platforms and operating systems, and self-aware networking and middleware infrastructure. The developed technologies are validated in three application domains: computational finance, distributed smart cameras and interactive mobile media systems.

Most networking performance enhancements occur through specific static solutions, where the structure of the protocol stack remains unchanged. Instead, we focus on a flexible software and hardware co-design for the entire protocol stack. In this paper, we present EmbedNet, a System-on-Chip implementation of a flexible network architecture for the Future Internet, where parts of the protocol stack can be moved between software and hardware at runtime. This enables the construction of dynamic protocol stacks that use available resources optimally.

Network programming is widely understood as programming strictly defined socket interfaces. Only some frameworks have made a step towards real network programming by decomposing networking functionality into small modullar blocks that can be assembled in a ?exible manner. In this paper, we tackle the challenge of accommodating 3 partially con?icting objectives: (i) high ?exibility for network programmers, (ii) re-configuration of the network stack at runtime, and (iii) high packet forwarding rates. First experiences with a prototype implementation in Linux suggest little performance overhead compared to the standard Linux protocol stack.

Future network architectures aim at solving the shortcomings of the traditional, static Internet architecture. In order to provide optimal service they have to adapt their functionality to different networking situations. This can be achieved by dividing the networking functionality into modular blocks and combining them as required at runtime. While the feasibility and flexibility of novel network architectures have been successfully demonstrated on software-based prototypes, they are often unable to provide sufficient performance due to the lack of hardware acceleration. We present a networking node architecture for future Internet applications that provides a reconfigurable hardware/software platform in which the modules of the node's network stack can be flexibly distributed at runtime across hardware and software. By utilizing novel reconfiguration-aware communication mechanisms for functional blocks both within and across the hardware and software domains, our flexible node architecture enables dedicated hardware acceleration for adaptive networking.