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Lulin Wide-field Telescope (LWT, with Minor Planet Center Observatory Code of D37) is a newly installed telescope at the Lulin Observatory. LWT consist of a 0.4m astrograph, with a focal ratio of 3.8, and a large format CCD, providing a ~2 degree squared field-of-view. LWT is joining the trend of automating telescopes in the world. Software packages that enable automatic observations for LWT include commercial software such as The SkyX, MaxIm DL and ACP Observatory Control Software (ACP), as well as in-house developed python codes. The Se python codes will generate an observing script executed by ACP to perform automatic observations. We presented the measured limiting magnitude of LWT. At an exposure time of 300 second, LWT can reach to a depth of 19.1 magnitude in V-band (under new moon). We also presented our successful efforts of tracking and follow-up observations of one near Earth asteroid, 2004 XP14, with LWT on 03 January 2019.

Frequency error, non-ideal channel estimation (CE) and inefficient seamless road side unit (RSU) service are critical issues occurring in conventional systems that are completely specified by current IEEE 802.11p standards. This study investigates novel techniques for achieving accurate frequency offset compensation and effective CE and RSU selection for handover in signal-overlapping areas. Recently, communications using data-aided orthogonal frequency-division multiplexing (DA-OFDM), such as pseudo-random-postfix OFDM and time-domain-synchronous OFDM (TDS-OFDM), have been actively studied because of their higher effectiveness, efficiency and better transmission quality. This study consists of three parts: (i) derivation of the maximum likelihood estimation for DA-OFDM, (ii) design of an accurate RSU selection scheme and (iii) implementation of a superior TD CE technique. Performance comparisons between the conventional and the proposed techniques are conducted through comprehensive computer simulations.

Wireless network authentication schemes have been researched forabout a decade, and associated security problems explored by manyresearchers. In 2004, Zhu and Ma proposed an authentication schemefor wireless environments. Afterwards other researchers proposedimprovements according to Zhu-Ma scheme. Mutual authentication isone of the most important issues. To the best of our knowledge,there is no scheme that allows a foreign agent to authenticate thehome agent and mobile user at the same time. Towards this purpose,we propose a simultaneous authentication scheme based on chaoticmaps, and describe how our proposed scheme addresses varioussecurity problems while maintain anonymity. DOI: http://dx.doi.org/10.5755/j01.itc.45.2.8875

Next-generation telematics solutions are being driven by the maturation of recently deployed intelligent transportation systems, assisted by the integration of and rapid collaboration with information communication technology markets and the automotive industry. Examples of this trend can be found in DSRC contexts in which Wi-Fi and WiMAX have become very relevant in vehicular environments. Comprehensive field trials were conducted and relevant measurements were collected in physical environments to investigate the possible environmental factors that occur in roadside-unit-to-vehicle communication scenarios. In these carefully controlled automobile experiments, the most representative parameters are measured and analyzed for DSRC in dynamic environments (e.g., packet loss, latency, and delay spread). Using a systematic testing procedure and through measurement analysis, the communication performance and the operating reliability of wireless communications can be effectively verified; insightful improvements and helpful suggestions and contributions may thus be achieved for telematics system designs. Furthermore, a practical, reasonable, and standardized testing procedure is proposed, and it can be utilized in equipment verification and product certification.

This paper presents a novel VLSI architecture for a fully parallel precomputation-based content-addressable memory (PB-CAM) with low-power, low-cost, and low-voltage features. This design is based on a precomputation approach that saves not only power consumption of the CAM system, but also reduces transistor count and operating voltage of the CAM cell. In addition, the proposed PB-CAM word structure adopts the static pseudo-nMOS circuit design to improve system performance. The whole design was fabricated with the TSMC 0.35-/spl mu/m single-poly quadruple-metal CMOS process. With a 128 words by 30 bits CAM size, the measurement results indicate that the proposed circuit works up to 100 MHz with power consumption of 33 mW at 3.3-V supply voltage and works up to 30 MHz under 1.5-V supply voltage.

In a typical wireless LAN application exploiting the OFDM technology, the preamble is usually used to acquire the channel state information in front of data payload. However, if the length of the frame is short, the bandwidth efficiency is restricted by the overhead due to the frame. For such an application that the length of the frame is long, we have to take into account the time-varying effect. In this paper, we study a semi-blind channel estimation method for improving bandwidth efficiency. Although the decision feedback method can be used for channel tracking, the well-known error propagation problem can seriously degrade the system performance. In our work, the semi-blind channel tracking method applies a decision error criterion to adaptively change the use of the error control signal between the constant modulus algorithm and the decision feedback in order to avoid the error propagation problem. Simulation results show that the proposed semi-blind channel tracking scheme has better BER performance than the decision feedback method.

Novel techniques of Road Side Unit (RSU) selection for handover were investigated in this study. It was determined that there are currently no efficient RSU selection schemes, which is a severe issue for conventional techniques following the current IEEE 802.11p standard. Recently, data-aided OFDM (DA-OFDM), such as Pseudo-Random-Postfix-OFDM (PRP-OFDM) and Time Domain Synchronous-OFDM (TDS-OFDM), have received attention because of their capability for higher effectiveness with better transmission quality. This study derived the maximum likelihood (ML) channel estimation for DA-OFDM and evaluated and compared proposed techniques by computer simulations.

Ever since the emergence of Intelligent Transportation System (ITS), there has been a rapid integration of communications and automotive electronics industry, promoting developments and trends for the new generation of telematics. Apart from the development and standardization of telematics, its field test is however attracting less attention while being a most important aspect of the issue. The purposes of this research are to set up software/field tests and propose possible improvements for IEEE 802.11p standard. Then, obtaining information from software simulation to establish a controllable field for ground tests, and analyzing the indicative parameters of packet loss and latency of Dedicated Short Range Communication (DSRC) telematics system under mobile conditions, to complete a systematic testing procedure, statistics analysis as well as a transceiver design that will improve the transmission performance.

This paper presents a novel 2/3 divider cell circuit design for a truly modular programmable frequency divider with high-speed, low-power, and high input-sensitivity features. In this paper, the proposed flip-flop based 2/3 divider cell adopts dynamic E-TSPC circuit that not only reduces power consumption, but also improves operation speed and input sensitivity. The whole design was implemented using the TSMC 0.18 μm 1P6M CMOS process. With an 8-stage 2/3 divider cell, the measurement results indicate that the proposed circuit operates up to 5.8GHz with the power-consumption less than 3.24mW.

A time-domain (TD) channel estimation (CE) technique is proposed in this paper to enhance the CE performance of IEEE 802.11p standards in cases when the pilot density is insufficient to accurately estimate channel states in rich-scattering environments. This technique is based on a least squares (LS) algorithm and assisted from Zadoff-Chu (ZC) sequences arranged into the symbol prefix and training preambles. The channel conditions tested in this paper were comprehensively simulated in urban, suburb and express-way scenarios.

A least-squares (LS) channel estimation technique is investigated to extend pseudo-random-postfix orthogonal-frequency-division multiplexing (PRP-OFDM) techniques onto mobile applications in rapidly time-variant frequency-selective fading environments. The proposed method exploits self-interference cancellation to effectively reduce a variety of interferences; and thus, it can overcome not only frequency-selectivity caused by multipath reception but also time-selectivity caused by mobility; in particular, OFDM communications are often expected to operate in the presence of both wide Doppler spread and long delay spread. As a result, the proposed technique can achieve lower channel estimation errors and lower bit error probabilities than the conventional techniques exploiting a time-averaging method. Since sufficiently long PRP sequences have never been found in the previous works regarding PRP-OFDM, an application of the proposed technique using chirp signals for mobile PRP-OFDM communication is investigated because the chirp signals exhibit good training properties.

In this paper, a novel logic gate design with low leakage is proposed. Traditionally, the subthreshold leakage through a logic gate depends on the applied input vector. In order to reduce leakage power, we stack an extra transistor in the large leakage path. The proposed structure induces low leakage current under all possible inputs. Compared to the conventional CMOS logic circuit design, the simulation results show that the proposed logic circuits not only reduce significant leakage power dissipation, but also keep similar circuit performance as conventional CMOS logic circuits

This paper presents a novel VLSI architecture for a fully parallel static type content addressable memory with low-power, low-voltage, and high-reliability features. In this paper, the proposed CAM word structure adopts a static pseudo nMOS circuit that not only improves system reliability, but also prevents using a clock signal to drive the overall system. In order to reduce static power occurring in the proposed CAM word structure, a precomputation approach is used to turn off a major part of the pseudo nMOS circuits. The whole design was simulated by HSPICE with the TSMC 0.35 /spl mu/m SPQM CMOS process. With a 128 words by 30 bits CAM size, the simulation results indicate that the proposed circuit operates up to 250 MHz with a power-performance metric less than 59 fJ/bit/search.

This paper presents a novel VLSI architecture for a fully parallel precomputation-based content addressable memory (PB-CAM) with low-power, low-cost, low-voltage, and high-reliability features. This design is based on a precomputation skill that saves not only power consumption of the PB-CAM system, but also reduces transistor count and operating voltage of the PB-CAM cell. In addition, the proposed CAM word structure adopts a static pseudo nMOS circuit design to improve system reliability. The whole design was fabricated with the TSMC 0.35 /spl mu/m SPQM CMOS process parameters under 3.3 V supply voltage. With a 128 words by 30 bits CAM size, the measurement results indicate that the proposed circuit works up to 100 MHz with a power consumption of less than 33 mW. Furthermore, the low voltage measurement results show that the proposed circuit works up to 30 MHz under 1.5 V supply voltage.

Sorting plays an important role in data and digital signal/image processing. We propose a sorter system architecture based upon a novel maskable WTA/MAX circuit design. The proposed sorter is able to sort an arbitrary N items of data with a simple control mechanism. No extra memory space is needed for storing temporary data during the sorting process. To achieve higher sorting speed, the proposed sorting system can be expanded easily by a simple hardware cascade. We use an 8-bit sorter design to verify our proposed architecture. A modular concept is adopted and the circuit interconnection is fairly regular. As a result, the bit-length of our proposed sorter can be easily augmented to 16-bit or 32-bit. The sorter chip has been manufactured by a TSMC 0.35 /spl mu/m 1P4M process with a 32 S/B package. Experimental results show that our chip functions correctly at 50 MHz at 3.3 V power supply voltage.

This paper presents a novel circuit for the pipelined and expandable sorting architecture that processes thirty-two 16-bit patterns at a time. This design is based on a compare-swap cell which can easily be cascaded to improve sorting performance. The sorting architecture combines suitable algorithm to sort arbitrary N data patterns. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The whole design was fabricated by TSMC 0.35/spl mu/m SPQM CMOS process. The estimation results indicate that the sorter can work up to 66MHz with the power consumption less than 20mW under 3.3V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors.

This paper presents a novel circuit for the k-WTA/Sorting network that processes eight 8-bit patterns. This design is based on a maskable WTA/MAX circuit which generates maximum value and winner with maskable skill. It can obtain the whole system functions: WTA/MAX/k-WTA/Sorter without adding any extra components. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The chip was fabricated with the TSMC 0.35/spl square/m SPQM CMOS process. Experimental results indicate this chip can work up to 66 MHz with power consumption less than 10 mW at 3.3 V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors.