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This paper presents the elimination of common mode (CM) conducted emissions in three-phase four-wire four-pole inverters connected to an AC distribution bus and operating in grid-following mode. Two novel control strategies are proposed and compared to the CM emission limits in the military standard 461G. Delta modulation and model predictive control both demonstrate elimination of the common mode voltage at the output of the three-phase four-pole inverter and the ability to meet the military standard’s requirements without a CM choke. The differential mode performance is comparable to that of three-dimensional space vector modulation, which does not cancel CM emissions. A physics-based model of the system was developed using state space equations to simulate the conducted emissions that can be expected with the two proposed methods. As the proposed methods result in increased switching frequency, wide bandgap devices were used to build a laboratory prototype, which successfully validate the simulated results.

A switching state selection scheme for a five level stacked multilevel inverter for open end winding motor drive is presented in this work. Using the proposed scheme, converter can be operated with a single DC supply and with zero common mode voltage. In addition, the switching transition of high voltage switches occurs at zero voltage conditions. The degree of freedom provided by the redundant switching states and voltage vectors of the inverter topology is utilised to design the modulation scheme. The proposed switching state selection leads to inherent capacitor balancing without using any extra sensors and fundamental frequency switching of the high voltage switches of the topology. The modulation scheme uses triangular carrier comparison and hence avoids the complexity of sub-sector identification and dwell time calculation. Half wave symmetry in output waveforms is ensured by maintaining synchronous sampling with constant samples per fundamental cycle. The inverter topology and the effectiveness of state selection scheme is experimentally validated on an open end winding induction motor drive and experimental results showing steady state and dynamic operation are presented.

In this paper, a new method is introduced for operation of three-phase symmetric cascaded H-bridge (CHB) multilevel inverter (MLI) after failure of power switches. When a switch fails, the faulty leg of the H-bridge is bypassed and the remaining leg is kept in use. Even with multiple faults in different H-bridge cells, the CHB is optimally reconfigured to continue its operation with its maximum healthy capacity. Based on the remaining operational part of the converter, a fault tolerant control scheme with zero-sequence voltage injection (ZSVI) is proposed to synthesize a balanced line-to-line voltage. Using this method, the post-fault line-to-line voltage of CHB is maximized with the minimum common mode voltage (CMV). Reduction of CMV is of importance in motor drive application. Also, fundamental component of CMV affects the real power of CHB phase legs. Through reducing the fundamental CMV, unidirectional power transfer from the dc side to the ac load is achieved in a wide operation region. The performance of the presented fault tolerant technique is verified in MATLAB/SIMULINK environment and validated on a three-phase 5-level hardware prototype

To balance the phase output currents of a multi- phase inverter, negatively coupled inductors (NCIs) can be used to achieve a larger differential mode (DM) loop impedance than the common mode (CM) loop impedance. For a good current sharing effect, the inductances of the NCIs should be large, leading to bulky size and cost ineffectiveness, which should be avoided in high-power applications. This paper proposes a novel current balancing method based on parallel resonance. A parallel resonant network (PRN) is inserted between any two phases. With -Y transform, the inductor common point and the capacitor common point are generated, either of which can be used as the CM output node. For a series-series compensated wireless power transfer system, part of the existing compensating capacitance can be employed to form PRNs with the added paralleling inductors. The DM currents are suppressed by the large impedance of the PRNs. Compared with the existing method, the inductances of the NCIs can be greatly reduced to achieve better current balancing performance. The added paralleling inductors are of small current ratings, which are only visible to DM currents. A prototype is implemented to validate the proposed method.

This paper proposes an intensive study for common-mode voltage (CMV) elimination/reduction in a five-level dual T-type multilevel converter (5LDT-MLC) drive. An advanced and fast model predictive control (MPC) approach is developed for CMV reduction (CMVR) and CMV elimination (CMVE) based on preselection of the switching states (SS). In addition, the proposed approach considers the torque control and the capacitor balancing of the proposed drive as essential aspects of MLC drives. A detailed study for the impact of the converter SS on the CMV is presented. The main features of the proposed MPC approach are reducing the complexity of the cost-function, the tuning burden of the weighting factors, and the computation time by more than 80% compared to conventional MPC techniques. A hardware implementation based on Silicon Carbide (SiC) T-type MLC is built. The experimental results demonstrate the effectiveness of the proposed MPC approach to mitigate/eliminate the CMV along with achieving the torque command and balancing the DC link capacitors. Unlike conventional CMVR techniques, the proposed approach reduces the CMV by 75% of its normal values without jeopardizing the harmonic contents, drive efficiency, and flux as well as torque ripples.

An integrated zero common mode voltage (ZCMV) modulation algorithm is developed in this research for dual-parallel neutral-point-clamped (NPC) inverters treated as an integrated system. While the conventional methods achieve CMV elimination with the cost of worse harmonic performance, the proposed method guarantees zero CMV and better current quality simultaneously by taking advantage of the extra space vectors provided by paralleling. Specially designed switching sequences are developed to maintain a balanced neutral point of DC-bus and ensure the averaged circulating current being zero, which is critical to the parallel operation and normal function of NPC inverters. In addition, although the switching sequence design is complicated, a simple approach is proposed and implemented on a commonly used digital signal processor (DSP). A laboratory prototype is also developed and used to test the system performance under steady-state conditions and dynamic process in grid-connected operation. Compared with conventional ZCMV modulation, experimental results verify the effectiveness of the integrated modulation in eliminating CMV, in addition to the dramatically reduced output current distortion.

Common-Mode Voltage Mitigation By Novel Integrated Chokes And Modulation Techniques In Power Converter Systems

In transformerless photovoltaic (PV) generation system, the neutral-point (NP) voltage balancing and the ground current reduction of three-level inverter are carefully regulated using space vector modulation (SVM) scheme. Nevertheless, in low-voltage ride-through (LVRT) operation, the simultaneous reduction of NP voltage oscillation and common mode voltage (CMV) has not been researched yet. To overcome these issues, a selective SVM (SSVM) strategy is proposed in this paper. First, the NP voltage oscillation of three-level inverter in LVRT operation is analyzed in detail, which reveals that the NP voltage is affected by phase currents and duty cycles. Based on the location of output voltage and the direction of grid currents, the correct small vectors are selected under different power factor angles. Then, the small vector force (SVF) including the grid currents and duty cycle on NP voltage is proposed for the first time. According to the value of SVF, the optimal small vector having the most effective impact on NP voltage among the correct vectors and switching sequence are determined. With the proposed method, the NP voltage oscillation and CMV are reduced simultaneously in LVRT operation. Finally, the effectiveness of the proposed method is verified with experimental results.

This paper presents a control method to balance, in average, the DC-link capacitor voltages while injecting power to the grid using an h-bridge neutral-point clamped five-level inverter grid-tied through an LCL filter. The method exploits the structure of a particular model representation of the system comprising a differential-mode part and a common-mode part, which turn out to be decoupled from one another. These decoupled representation enormously facilitates the control design as it can be performed as two independent processes as well. The first design process involves the differential-mode model part and focuses on the grid current injection, while the second design process focuses on the balance of the DC-link capacitors voltages, and is based on the common-mode model part. Out of this, two control components are derived, namely differential-mode and common-mode control components, which are later recombined to form the two control signals, one per inverter branch, required as references in a conventional modulation algorithm to generate the switching sequence. Numerical and experimental results are performed to evaluate the performance of the proposed controller for the h-bridge neutral-point clamped inverter subject to those interconnections.

Three-level inverter has been widely used in electric drives and renewable power generation system. However, the common mode voltage (CMV) and output current ripple reduction of three-level inverter should be carefully regulated for the appropriate operation. As these two targets are mutually interrelated, the conventional space vector modulation (SVM) scheme cannot cope with them decently. To overcome this drawback, this paper proposes a novel modified SVM scheme to realize CMV and current ripple reduction simultaneously. The generating mechanism of output current ripple is analyzed, and the relationship between current ripple and utilized vectors is quantitatively described. Based on the analyses, the proposed optimal current ripple and CMV reduction pulse width modulation (OCR-CMVRPWM) method adopts four voltage vectors (large, medium, small and zero vectors) to reduce root mean square (RMS) value of current ripple by allocating the sequence and dwell times of utilized vectors. Compared to the existing PWM methods, the proposed OCR-CMVRPWM scheme can reduce the peak of CMV to half of value using the conventional SVM, and obtain a significant reduction of output current total harmonic distortion (THD). The effectiveness of the proposed method is validated by both simulation and experimental results.

A non-isolated fast charger is proposed for electric vehicle (EV) battery system. The leakage current can be reduced by the novel charging system without bulky transformer. A zero sequence voltage control method is developed to stabilize the common mode voltage thus reduce the leakage current. The proposed fast charger includes two energy conversion stages: DC/DC converter for battery side control; DC/AC converter for grid interface and common mode voltage control. The parameters of the system with LCL filter are analyzed and optimized for a better performance of grid interface. Grid service functions are designed for the fast charger to provide grid voltage/frequency compensations. High power (22kW) and high efficiency 99% are achieved with low leakage current 20mA. The experiments are implemented to verify the proposed fast charger system.

In this paper, balance technique is applied into two-channel interleaved three-phase acdc converters with critical conduction mode based soft switching modulation. By adding additional inductors and coupling them with the original ones, the realization of the balance becomes possible with proper design; thus reducing the common-mode (CM) EMI noise. The balance condition is derived, and the impact of balance technique on the circuit operation especially on the switching frequency variation is quantified in order to provide the design guideline. Based on the application of balance technique, instead of the commonly used litz-wire based inductors, PCB winding coupled inductors are adopted and designed to effectively achieve the reduction of CM EMI noise. The design methodology and process are presented, and the design trade-off is made between the inductor loss and the inductor footprint. Finally, the effect of CM EMI noise reduction and the system efficiency with balance techniques and PCB winding magnetics are tested on a 25-kW SiC-based soft-switching three-phase acdc converter prototype.

As the increase of power and voltage level of back-to-back three-level NPC converters, the high-amplitude and high-frequency common-mode voltage (CMV) has become an urgent problem. To address this, a CMV elimination method based on PWM pulse alignment for back-to-back three-level NPC converter is proposed. On this basis, a neutral-point potential balance method based on zero-sequence voltage (ZSV) is also proposed. In order to decouple the CMV elimination and the neutral-point potential balance, a same optimal ZSV is injected into both the rectifier and inverter sides and the CMV elimination will not be affected. Simulation and experiments are presented to verify the effectiveness of the proposed method.

Multiphase space vector pulsewidth modulation (SVPWM) method has gained much attention with the growing interest in multiphase motor drives. Conventional multiphase SVPWM becomes more complex with the increase of phases, while simplified multiphase SVPWM is required for industrial applications. In addition, common-mode voltage (CMV) is the main cause of motor bearing damage and winding insulation breakdown for electrical drives. In this article, a simplified and generalized SVPWM method with CMV reduction is proposed for multiphase drives. The proposed SVPWM is intuitive and universal for arbitrary two-level multiphase inverters with odd phases, and CMV is restricted within ± V dc/2 N ( N is phase number). Experimental results verify theoretical analysis and effectiveness of the proposed method.

In this paper, a single-layer planar single-ended-tobalanced crossover has been proposed, which has a wideband filtering differential-mode response, wide path-isolation bandwidth, and an excellent common-mode suppression. The complete design procedure and rigorous derivations are demonstrated based on the even-/odd-mode analysis. A 3.5 GHz prototype has been designed, simulated and measured. Finally, the measured 15-dB differential-mode filtering bandwidth and 10-dB common-mode transmission bandwidth are 37.38% and 77.33%, respectively. Besides, a 117% bandwidth of 10-dB path-isolation is also achieved. Moreover, the bandwidth of 22-dB common-mode-to-differential-mode conversion is 143% over the frequency range of 1-6 GHz. This proposed crossover can be an excellent candidate for constructing balanced and unbalanced wireless communication systems.

This article proposes new common ground bridgeless power factor correction rectifiers suitable for use in any application which requires a positive or negative dc power supply. The main advantage of the proposed rectifiers, compared to previous works, is the provision of the common ground between input and output, which eliminates electromagnetic interference (EMI) associated with high rates of change of voltage and consequently reduces the need for EMI common mode filtering. The converter also provides step-down and step-up operation, and facilitates positive or negative output voltages with a low number of semiconductor devices operating simultaneously. High power factor, acceptable grid-side current quality, and high efficiency are also achieved. Two variants are presented, referred to as type-I and type-II, which offer common ground positive and negative dc voltages, respectively. Closed-loop control of the converters is provided by a dead-beat current controller in the inner loop. Experimental results are presented for a 500-W prototype, operating from 220 and 110 Vrms input to $\pm$ 48 and $\pm$ 200 Vdc output. The experimental results demonstrate the capability for step-down and step-up ac-to-dc power conversion with a peak efficiency of 96.8% and 96.6% in the positive and the negative outputs, respectively.

Impedance-source based solar PV systems are capable of achieving both voltage boosting and inversion in a single stage, resulting in a simple design thereby enhancing reliability. One of the major concerns of PV systems is their leakage current, as it can cause hazardous operational insecurity and reliability. This paper introduces a quasi Z-source based five-level inverter, which displays the following advantages: (i) reactive power handling capability, (ii) single-stage boosting, (iii) shoot-through immunity, and (iv) reduced leakage current based on VDE 0126-1-1. The proposed single-stage power converter is constituted by the fusion of a boosting stage, consisting of two back-to-back connected quasi-Z-sources, with a 5-level inverter produced by the combination of T-type and neutral point clamped (NPC) arms. The problem of the leakage current is addressed by a modified modulation technique and a passive filter structure, which filters high frequency variations in the common mode voltage (CMV). The working principle of the proposed power converter and the effectiveness of the modulation scheme to reduce the leakage current are assessed with the aid of simulation studies in both stand-alone and the grid-connected modes. The simulation results are experimentally validated with the aid of a laboratory prototype of 500 W rating.

The insulation monitoring technique for converter transformers has been explored using characteristic harmonics in the voltage source converter (VSC) system by the authors. The previous work enables the monitoring of aged groundwall insulation but cannot cover other insulation components. In order to explore the possibility of multitype insulation aging monitoring, in this article, we first derive an advanced model considering unevenly distributed circuit parameters along transformer windings and their frequency-dependent feature. Model improvements provide an accurate tool to describe multitype insulation in a wide frequency range. Based on the advanced model, a novel wideband common-mode (CM) impedance-response-based monitoring strategy for the VSC-connected transformer is proposed to achieve the evaluation of the aging in different insulation components. An illustrative case is studied on a 15 kVA transformer driven by an industrial inverter. Offline and online experiments are conducted to prove the effectiveness of the advanced model and the proposed strategy. Compared with the existing methods, the CM impedance-response-based strategy enables the online monitoring of multitype insulation components in an effective and noninvasive manner. In addition, the aging severities can be estimated reliably, even at incipient stages.

In ac–dc power conversion system, modular multilevel converter (MMC) has been a promising technology, especially for high-voltage application. In such kind of application, the common-mode voltage (CMV) generated by power electronic switching can cause damage to electrical components and increase the electromagnetic interference (EMI) to the system. Hence, this article proposes a modulation scheme to reduce the CMV of MMC applied in high-voltage system, such as high-voltage dc. Usually, MMC consisting of numerous submodules (SMs) adopts the nearest level modulation (NLM) with the low switching frequency, so the CMV of the NLM scheme is analyzed, which indicates that the peak value of CMV is one-third of SM voltage. If one more or one less SM is turned on compared with NLM, the CMV caused by modulation can be eliminated theoretically. Subsequently, a modulation scheme based on the nearest zero CMV vector (NZCMVV) to reduce CMV is proposed for MMC. The NZCMVV scheme utilizes the two adjacent levels as candidate levels, and the theoretical ZCMVVs are picked out. Finally, the ZCMVV closest to the reference vector is selected to approximately replace the reference. The proposed method is simple and easy to implement. Simulated and experimental results validate that the proposed scheme can reduce CMV and CM current compared with the traditional NLM method.

Designing an efficient, compact, and optimized electromagnetic interference (EMI) filter for the next generation high-frequency switched mode power converter while maintaining a small form factor with high power density, requires adequate research and development effort. This article presents a systematic as well as unified approach to design the EMI filter for any power electronic converter, particularly for three-phase ac–dc active boost rectifier systems. Since the differential mode (DM) filter stage consumes a major part of the EMI filter volume and weight, DM filter design optimization is a necessary yet challenging task to attain a higher power density. This article theoretically demonstrates the design steps for choosing the appropriate filter component values and number of filter stages to achieve the smallest volume of the DM EMI filter. Furthermore, to design an optimized common mode (CM) filter stage, a research effort has been made for estimation of the CM noise corner frequencies followed by multiconstraint volume optimization through a detailed mathematical noise modeling of the converter. While the validation of the proposed design methodology is done through MATLAB simulation, an experimental verification is also performed by designing the optimized EMI filter for a 2.3-kW proof of concept of a three-phase boost power factor correction converter to comply with the stringent EMI requirements of DO-160F standard.

Virtual space vector pulsewidth modulation (VSVPWM) provides a new approach to neutral point voltage (NPV) control and common mode voltage (CMV) suppression. Few values of coefficients configured in the virtual vectors cannot adjust the NPV continuously. An improved VSVPWM (IVSVPWM) with active neutral point voltage control (ANPVC) and CMV suppression is proposed in this article. Continuously variable coefficients configured in the virtual vectors adjust the NPV actively and continuously for any load power factor over the full modulation indexes. Failure of CMV suppression is analyzed, and the undesired vectors with high CMV are avoided by limiting the range of the variable coefficients. The limited variable coefficients and the selected basic vectors with low CMV suppress the CMV effectively. Simulation and experimental results are given to validate the proposed novel IVSVPWM, which can achieve quicker ANPVC and reduce CMV to half of the conventional VSVPWM simultaneously.

This paper presents Space Vector Modulation (SVM) sequences that reduce Common-mode Voltage (CMV) in Dual Three-phase Asymmetrical Induction Motor (DTAIM). First, existing SVM techniques namely Standard SVM (SSVM) and CMV1 are studied and then, three new switching sequences CMV2, CMV3 and DCMV3 are proposed which reduce peak magnitude of CMV by 66.8% in comparison with SSVM technique. In SVM techniques, to obtain least CMV, zero vectors are usually replaced by two opposite large Active voltage Vectors (AVs) with equal time duration. In such topologies like CMV1, total six AVs are utilized to synthesize reference vector. The proposed CMV2 utilizes only five large AVs to synthesize reference vector and reduces CMV. Selection of five neighbouring AVs in proposed techniques yields reduction of harmonic flux trajectories and stator current ripple. Additionally, two more switching sequences (CMV3 and DCMV3) are developed that is related to utilization of specific zero voltage vectors in all sectors (7 and 56) and produce zero CMV. The CMV and stator current ripple are considered as performance parameters for different SVM techniques. All SVM techniques are analysed by analytical results, computer simulations, and using prototype test setup of DTAIM fed by Dual Three-phase Voltage Source Inverters (DTVSIs).

An improved two-stage model predictive current control (MPCC) for three-phase three-level converters in the paper, which can simultaneously achieve common-mode voltage (CMV) reduction, effective dc-link capacitor voltage control, and decreased computational burden, is proposed. Compared to the other current control strategies, it has the capability of handling multiple control objectives and possesses a simple structure. Furthermore, it greatly reduces the CMV since the peak CMVs of all the candidate voltage vectors are constrained to be less than one sixth of the dc-link voltage. In addition, an optimal two-stage voltage vector selection mechanism is employed in the proposed method. It helps to significantly reduce the computational complexity. Simulation and experimental results are provided to verify the effectiveness of the proposed method.

The modulation strategies of dual active bridge (DAB) including single phase-shift (SPS), dual phase-shift (DPS), and triple phase-shift (TPS) have been proposed to optimize the efficiency, eliminate the reactive power, and release the current stress. While the previous literature focuses on the accurate loss model in steady states or small-signal analysis for dynamic response, the common-mode (CM) model has been largely ignored. The main contribution of this article then is to propose an analytical CM model for DAB, which considers the CM parasitic capacitors including those of grounded heatsink and transformer windings. Based on such model, the CM performance is compared among different modulation strategies. The impact of two H-bridge on the input and output CM voltage has been addressed. A prototype based on SiC devices is used to verify the proposed analytical mode under SPS, DPS, and TPS. It is found that while TPS improves the light-load efficiency it introduces the worst CM noise. Influence of the ZVS current setting on the CM performance is also discussed.

Transformer-less inverters (TIs) are widely used in photovoltaic (PV) applications owing to their low cost and high efficiency. However, the combined effect of high-frequency common mode voltage and PV parasitic capacitance burdens the TIs with undesired ground leakage current. In this article, a switched capacitor (SC)-based five-level TI is proposed. The negative dc rail of the proposed TI is directly connected to the grid neutral, thereby completely eliminating the leakage current. Besides, it has the inherent capability of boosting the output voltage without using any magnetic component or additional circuitry. For several instances in every fundamental cycle, the SCs are paralleled with the input voltage source and hence are self-balanced. The proposed topology does not have any limitation on modulation index since the SC voltages are self-balanced and hence less complex or no dedicated control scheme is required. Further, a quantitative comparative study is presented, highlighting the benefits of the proposed TI regarding boosted voltage, elimination of leakage current, and reduced component count. Finally, in order to verify the performance of the proposed TI, detailed simulations followed by experiments on a laboratory prototype developed by using DS1202/1302 dSPACE controller are carried out and the results presented for both steady-state and dynamic conditions verify the feasibility of the proposed TI.

This article proposes a new pulsewidth modulation (PWM) strategy to reduce common-mode voltages (CMVs) in grid-connected two-level inverters. Reduction of CMVs is an important issue in the field of distributed energy resources (DERs) because CMVs at a high switching frequency cause ground leakage currents that lead to safety issues in the applications of DERs. In the proposed PWM strategy, each reference vector is split into two vectors during the PWM period. The peak-to-peak magnitude of CMV is reduced by one-third as the split vectors are synthesized without using zero vectors. The influence of the dead-time and its compensation in the proposed method are also described. Our proposed method can be easily implemented with carrier-based PWM. Simulation and experimental results are presented to verify the performance of the proposed strategy.

A three-phase three-level converter with an LCL filter has been used in the industry because of its low switching harmonics. However, it inevitably suffers from dc neutral-point imbalance, which may unnecessarily stress semiconductors and deteriorate power quality. The imbalance will, nevertheless, naturally rebalance, but it usually takes a long time. A common rectification is, thus, to add an active or a passive booster to speed up the balancing. An active booster requires sensitive sensors and control modification, which will increase the system cost and complexity. A passive booster is, therefore, preferred owing to its exemption of monitoring and control efforts. The existing three-phase passive booster, however, contains several extra separate LC components, which are normally not functioning during the balanced conditions. They should, hence, be reduced. One approach is to dual use the existing LCL (or other high-order) filter for both harmonic filtering and dc-link balancing. Topologically, it requires only the addition of one extra capacitor along the return common-mode path. Using newly formulated criterions related to sizing, harmonic, and modulation selections, the balancing performance of the resulting capacitive balancer has been evaluated comprehensively. Finally, an experimental prototype is built for testing the balancing mechanism under different operating conditions.

Many reduced common mode voltage (CMV) modulation methods have been proposed for three-level inverters. However, most of them suffer from large current distortion because only part of the available base vectors is utilized. The interleaved paralleling can reduce both CMV and the output current distortion, though the CMV reduction is limited and large zero-sequence circulating current (ZSCC) is inevitably caused by the phase-shifted carriers. To further reduce the CMV while maintaining smaller current distortion and ZSCC, a five-level reduced CMV (RCMV) modulation method is proposed in this article, which treats the parallel inverters as a whole. Theoretical analysis reveals that the integrated modulation provides additional base vectors that contribute to smaller total harmonic distortion (THD) of the current, and the selected vectors ensure the nearest-three-vector synthesis and half-reduced CMV. The switching sequences design and neutral point balancing strategy are also developed for dual-parallel three-level inverters, ensuring that the average circulating current is zero and the neutral point voltage is balanced, which are both critical to the proper operation of parallel inverters. Superior performance in terms of CMV, THD, and ZSCC provided by the proposed method in comparison with conventional modulation is verified by comprehensive simulation and experimental results.

The common‐mode inductor (CMI) is a very interesting device used to reduce electromagnetic compatibility and electromagnetic interference problems. When considering the performance of an electrical device, it focuses on the differential‐mode voltage and current. Common‐mode voltages and currents can lead to several system problems. The common‐mode current is the sum of the currents in the conductors of the set. It often leads to electromagnetic noise, which can degrade the performance of sensors and cause low‐voltage control hardware to fail. The common‐mode equivalent circuit is a useful tool in understanding a system's common‐mode behavior. The impact of asymmetry is that the differential‐mode currents will create a voltage term in the common‐mode equivalent circuit. The chapter considers the magnetic analysis of the CMI. The CMI current has two components: the differential‐mode current, and the common‐mode current. The chapter develops a design paradigm for the CMI.

The three-level inverter has been widely researched and adopted in industry. This article further proposes a carrier-based modulation method to reduce the common-mode voltage (CMV) and obtain high-quality output currents for three-level inverter with unbalanced neutral-point voltage conditions. In this method, the zero-sequence voltage is calculated by three-phase modulation waves, three-phase output currents, and voltages across the dc-link capacitors. The limitations of the zero-sequence component are carefully considered in order not to generate the basic voltage vector with high CMV magnitudes. In addition, a deadbeat control scheme for controlling the dc-link voltages asymmetrically with the proposed pulsewidth modulation method is presented, and asymmetrical control of dc-link voltages can be realized with fast response. Compared with the conventional space vector modulation (SVM) and the virtual SVM methods, the proposed scheme can reduce the CMV by half. Simulated and experimental results validate the effectiveness of the proposed method.

The matrix converter (MC) is often projected as a substitute to voltage source converter due to its numerous advantages, especially in converter fed drive systems, where features like bidirectional power flow, common mode voltage (CMV) elimination, improved source, and load side current quality, are highly desirable. This article presents the speed encoderless control of an induction motor, with the exclusive use of only six switching states of MC that generate zero CMV. The use of only these six states, contrary to the 27 (or 21) states used otherwise, also ensures reduced processor burden. For the control of both source, and load side parameters, multiple objective finite set model predictive control (MO-FS-MPC) is used. MO-FS-MPC is conventionally associated with cumbersome weight tuning, which is eliminated by undertaking a fuzzy decision making approach. Furthermore, a full-order predictive model of an induction motor is used for the prediction of flux, and stator currents, allowing control down to zero motor speed. For the estimation of motor speed, the mechanical model of the motor is used, such that parameter drift is significantly overcome through suitable compensation of the error between predicted, and sensed stator currents.

This paper proposes the reduction of common mode voltage (CMV) magnitude using a simplified logical modulator (SLM). This modulator uses the ideas of space vectors to detect and eliminate the high common mode vectors produced by carrier phase-shifted sine pulse width modulation generator. The proposed SLM has an inherent ability to eliminate the CMV spikes due to dead time, but it introduces short circuit vectors (SCVs). This issue is addressed by designing an SCV eliminator (SCVE). The performance of the SLM-SCVE is validated through simulations. The proposed SLM-SCVE is implemented using MATLAB—Xilinx system generator interface in Spartan 3E–FPGA and tested in a prototype hardware. The proposed SLM-SCVE proves to be a simple and reliable solution for the reduction of CMV in industrial application because finite number of logic gates is used.

The winding impedance spectrum method becomes popular in online stator insulation monitoring in recent years. It can detect the insulation ageing condition and give alarm before catastrophic failure happens. However, the theoretical explanation of this method is not sufficient and the relationship between impedance spectrum and insulation ageing is not clear. In addition, the existing methods need additional signal injection equipment, which is intrusive and difficult to be applied in industrial applications. Therefore, this article develops a noninvasive interturn insulation condition monitoring method based on the common-mode impedance spectrum in inverter-fed machines. By building a broadband stator winding insulation model, the relationship between the interturn insulation ageing and the impedance spectrum is studied and the high frequency parallel capacitance is first proposed as an indicator for the interturn ageing. The offline test validate the effectiveness of the proposed method and the online test shows the potential of this method for noninvasive condition monitoring in inverter-fed machines. Future work is planned to further improve the online performance of the proposed method.

In this article, a generalized selective harmonic elimination pulsewidth modulation (SHE-PWM) formulation with common-mode voltage (CMV) reduction ability for multilevel converters (MLCs) is presented. The CMV is suppressed by regulating the low-order dominant zero-sequence harmonics (ZSHs) of the three-phase SHE-PWM waveforms. Two formulations are included in the proposed model to achieve the full range operation objective, i.e., with zero low-order ZSHs in low and medium modulation index ( ma ) range and with an optimal third-harmonic injection in high ma range. With the proposed formulation, the amplitude of CMV can be effectively reduced for all types of MLCs over the whole ma range. Besides, two kinds of solving algorithms, i.e., off-line and real-time based, are introduced to provide efficient solution tools targeted at the proposed model. In this article, a case study with three-level neutral-point clamped inverters is discussed in detail to better illustrate the proposed formulation and the coupling effects between the CMV reduction and capacitor voltage balancing objectives of MLCs. Simulation and experimental results based on multiple MLC topologies are carried out to validate the effectiveness of this generalized SHE-PWM formulation with reduced CMV values.

The concept of open-current vector for sparse matrix converter is put forward along with its application constraints in this article. Based on the open-current vector, an improved space vector modulation (SVM) strategy is proposed to reduce the peak magnitude of common-mode voltage (CMV) by 42.3% without sacrificing the performance of input and output waveforms and the voltage transfer ratio (VTR). First, the application constraints and common-mode equivalent circuit of the open-current vector in the rectifier stage of the sparse matrix converter are analyzed. After that, in accordance with the principle of minimum switching action and two adjacent active vector synthesis, the improved SVM strategy used a suitable open-current vector instead of the active-current vector in the rectifier stage when the zero-voltage vector is used in the inverter stage, which contributes to CMV reduction. The improved SVM strategy not only reduces the peak magnitude of the CMV, but also ensures that the performance of input and output waveforms and the VTR are the same with those of traditional SVM. Finally, the effectiveness of the improved SVM strategy is verified by simulation and experiments.

This letter proposes a four-leg current-source inverter (CSI) fed three-phase motor drive. Different from the previous four-leg CSI inverter, the proposed configuration introduces the fourth leg in CSI, which connects to the neutral point of the motor through an extra output filter capacitor. Therefore, the proposed configuration can not only reduce the common-mode voltage (CMV) under the normal condition, but also provide the fault-tolerant operation ability under open-circuit faults in windings and switches. The dedicated space vector modulation (SVM) strategies have been designed. Compared with prior research on CMV reduction, the four-leg method has the full range of modulation index and will not increase any harmonics in the currents. Meanwhile, the fault-tolerant ability is offered, which can further enhance the reliability of the motor drive. A laboratory prototype has been built to experimentally verify the effectiveness of the proposed motor drive topology and the control schemes.

In the motor drive system fed by multilevel inverter, the problems such as the complexity of reference voltage synthesis, high common mode voltage (CMV), and high switching loss are usually the obstacles to the practical application. In order to reduce the computational complexity and improve the performance of permanent magnet synchronous motor (PMSM), a novel space vector pulsewidth modulation scheme, which is practical and independent of level number is proposed for PMSM vector control. First, the space vector plane is redivided, and the coordinates of the nearest three vectors and their duty cycles can be obtained directly by determining the location of reference vector, which simplifies the calculation and does not need any iterative algorithm. Then, the optimal switching state and switching sequence are selected online so as to ensure the minimum switching loss under the premise of minimum CMV. This article provides an original method and new idea for motor drive system fed by multilevel inverter. Finally, the practicability and validity of the proposed method are verified by simulation and experiment.

Single-phase symmetrical five-level converter offers a low-harmonic power interface, whose attractiveness is nevertheless affected by dc-link voltage imbalance. Fast rebalancing methods have therefore been proposed, if the natural balancing speed of the converter is intolerable. One possible method is to add a separate parallel RLC branch between the converter and its filter. Being parallel, the branch does not change spectral properties of the converter and filtering properties of the filter, in addition to its robust sensor-less requirement. However, being separated, it does not properly integrate with the filter to explore dual usabilities of the components. This article therefore proposes a few differential-mode (DM) filters with each having a common-mode (CM) capacitor as the balancing accelerator. The accelerator does not conduct and hence consume no power during the normal balanced condition. It conducts only when an imbalance occurs and directs only those harmonics with fast balancing ability to the dc link. Its design is simple and can conveniently be performed with an appropriate CM harmonic model. Its performance has ultimately been verified by simulation and experimental results obtained with two different modulation schemes.

The high-frequency zero-sequence circulating current (HFZSCC) is generated when the carrier phases are different in a parallel rectifiers system. Therefore, a modified LCL filter is adopted to suppress the HFZSCC. Nevertheless, the internal common mode resonance current (ICMRC) and external zero-sequence resonance circulating current (EZSRCC) are produced, which causes system instability unavoidably. Since these two issues are coupled with each other, the conventional resonance currents control methods reported so far cannot address them properly simultaneously. To suppress ICMRC and EZSRCC, a detailed model analysis of internal common mode current and zero-sequence circulating current (ZSCC) are presented, which reveal the ICMRC and EZSRCC are related to capacitor-side ZSCC (CSZSCC). Then, based on the model, in this article, the controller of CSZSCC is presented to suppress ICMRC and EZSRCC. Additionally, a closed-loop controller is designed to reject disturbances of low-frequency zero-sequence circulating current (LFZSCC). It is realized by adjusting the duty cycle of the small vectors in each pulsewidth modulation sampling period. As a result, HFZSCC, ICMRC, EZSRCC, and LFZSCC are mitigated with the proposed scheme, thus, improving the quality of the input currents. Simulation and experimental results verify the effectiveness of proposed method.

As conventional transformerless PV grid-connected inverters have shoot-through problem and common mode leakage current issue, a doubly grounded transformerless PV grid-connected inverter is proposed. The proposed inverter consists of a buck converter and a buck–boost converter, which operates at positive and negative half-line cycles, respectively. There is no shoot-through problem in the proposed inverter, so dead-time in gate signals is not required. As grounds of the PV array and the grid are shorted, the common mode leakage current can be eliminated. No current flows through the body diodes of switches, so there is no reverse recovery issue of the body diodes of switches. Only one switch operates at high frequency in each half-line period, so efficiency of the system is improved. Operating principle of the proposed inverter is elaborated in detail. The control strategy is given. The control method is simple and the grid-connected inverter is a single-stage system in each half-line cycle. Loss calculation and example is given in detail. Finally, simulation and experimental results of the proposed inverter validate the theoretical analysis.

This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple comparators to reduce the SAR loop delay. Offset mismatch between the comparators severely degrades the effective resolution. This paper addresses the common-mode voltage variation in the LU-SAR architecture due to comparator kickback and the problems related to the common-mode dependency of the comparator offset. The proposed offset calibration scheme ensures that the comparators are calibrated at the same input common-mode voltage at which they each operate during the SAR conversion to prevent the common-mode dependent offset mismatch between them. Moreover, the proposed ADC design exploits the common-mode variation immunity of the proposed calibration scheme to optimize the figure-of-merit (FoM). The prototype ADC manufactured in 28nm FDSOI CMOS achieves 42.57dB signal-to-noise-and-distortion ratio and 22.8fJ/conv.-step FoM at 800MS/s with near Nyquist frequency input, and occupies an area of 0.0037mm(2).

This paper proposes a common‐mode voltage injection‐based pulse width modulation strategy to optimize the AC current ripple of parallel interleaved converters. In general, modulation methods entail a trade‐off between switching times and voltage error. Given the redundancy in the available vector sequences, we sequentially minimize the switching times and the voltage error. Specifically, we propose eight candidate vector sequences with minimized switching times for each 60° sector. Then, we quantitate the current ripple introduced by the eight vector sequences, and according to the calculations, we split each 60° sector into eight subsectors, each employs the respectively optimal vector sequence with the minimized current ripple. For implementation, the candidate vector sequences are further unified by a common‐mode voltage injection scheme. The injection depends on the momentary subsector in which the reference lies. Despite the complex geometry of the subsectors, we propose a simple decision procedure that can be easily implemented in mainstream microcontrollers. Compared to the conventional methods, the proposed common‐mode voltage injection‐based pulse width modulation has a smaller AC current ripple at the same switching loss. The experimental results verify the theoretical analysis and the effectiveness of the proposed common‐mode voltage injection‐based pulse width modulation strategy.

The performance of a current source converter (CSC) is greatly affected by its adopted modulation schemes. Among various modulation schemes, the carrier-based pulsewidth modulation (CB-PWM) has gained increasing attention owing to its inherent autosequencing process. However, existing CB-PWM schemes suffer from either high switching harmonics in ac current or high low-order common-mode voltage (CMV), and sometimes, both, which restrains the application of this promising scheme. To address this issue, this article explores the modulation mechanism of CB-PWM for a CSC. Based on that, this article proposes a direct CB-PWM scheme. Its implementation, mechanism, and characteristics have been developed and presented in detail. It is shown that the proposed scheme enjoys inherent low switching frequency, easy implementation, as well as high dc current utilization. More importantly, compared with existing CB-PWMs, the proposed scheme can simultaneously reduce the switching harmonics of ac current and the low-order CMV for a CSC. These superior performances can bring potential benefits to scale down the ac filter and common-mode choke for practical CSC applications. Effectiveness of the proposed scheme is verified experimentally with a CSC operating as an inverter.

A new design approach of developing multi-band balanced-to-single-ended (BTSE) power dividers is presented in this brief. The design is based on flexible coupling schemes which can guide designing multi-band balanced-to-single-ended power dividers with arbitrary number of bands and controllable bandwidth. Microstrip-to-slotline transitions are used to suppress the transmission of common-mode signals at all frequencies, which lead to an ultra-wide bandwidth of common-mode suppression. Slotlines play a critical role for they have two functions, one is to control the external coupling between ports and resonators, and the other one is to prohibit the propagation of common-mode signals. Based on the design approach, a dual-band and a tri-band balanced-to-single-ended power divider are modeled and simulated in the full-wave simulation environment. Prototypes are fabricated and tested, and the experimental results demonstrate that dual-band and tri-band filtering responses are realized in BTSE power dividers successfully. Moreover, the common-mode suppression and mode conversion levels of both designs are less than −29.5 dB at all frequencies (common-mode suppression fractional bandwidth is 200%), which is extremely desired in balanced circuits and systems.

In the open-end winding permanent magnet synchronous motor (OEW-PMSM) with common DC link, the common-mode voltage (CMV) will cause leakage current and zero-sequence current, which will lead to the decrease in the system life and efficiency. To solve this problem, the loop characteristics of leakage current and zero-sequence current were analyzed, and the condition for eliminating the leakage current and the zero-sequence current was deduced. Then, the CMV of the voltage vectors for the OEW-PMSM system was calculated, and the appropriate voltage vectors satisfying the conditions were selected to form the control vector sets. Combined with the model predictive torque control (MPTC), a cost function without the weight factor was proposed. The voltage vector sets were predicted by the cost function. The optimal voltage vectors were selected to control the OEW-PMSM, which can eliminate the leakage current and the zero-sequence current caused by the CMV. The effectiveness of the proposed method was verified by the simulation results.

Training the weighting factors of model predictive control in multiobjective problems is a time consuming and sophisticated process. In this article, conventional model predictive control (CMPC) has been developed as supervised learning model predictive control (SLMPC) to cancel common-mode voltage (CMV) in a three-phase neutral-point-clamped (NPC) inverter, while other control objectives are desirably tracked. SLMPC is accurately and quickly trained through the artificial bee colony (ABC) algorithm to optimize the controller weighting factors. Using the optimized weighting factors, transient response is minimized and CMV is surpassed. After training the weighting factors, SLMPC containing the optimized waiting factors is applied to the three-phase NPC inverter without considering the ABC algorithm in the control loop. By applying the optimized weighting factors to the cost function, SLMPC has been evaluated under several experimental and simulation tests to show that desired control objectives, particularly CMV suppression, have been attained. The proposed training process can be generalized and used for MPC cost functions with more control objectives to obtain the best possible performance.

This article proposes a new nine-arm modular multilevel converter (9A-MMC) with improved hybrid submodules for middle arms. In specific, the middle arms are formed by the unidirectional current full-bridge submodules (UC-FBSMs), while the upper and lower arms are formed by the traditional half-bridge submodules (HBSMs). Compared with the standard 9A-MMC where the upper, middle, and lower arms are all formed by HBSMs, the dc-side voltage of the new 9A-MMC can be reduced by one-third, and whose switch count is the same as that of the standard 9A-MMC. Moreover, the dc offset in the common mode voltages (CMVs) of the new 9A-MMC is eliminated. In this article, the middle arm current of the new 9A-MMC was thoroughly discussed, and the maximum operation range of the new 9A-MMC was also presented. To enlarge the operation range of the proposed 9A-MMC, a middle arm current reshaping control method was put forward as well. The feasibility and performance characteristics of the proposed 9A-MMC were finally verified by the simulation and experimental results.

Model predictive current control (MPCC) schemes have been considered as a promising control technique for voltage source inverters (VSIs). However, the computational burden reduction, harmonic currents elimination, and common-mode voltage (CMV) mitigation are special issues when MPCC schemes are applied to five-phase VSIs. Moreover, it is time-consuming to tune weighting factors for the multiple control objectives. To address these problems, this article proposes two computationally efficient MPCC schemes based on virtual voltage vectors ( $\text{V}^{3}\text{s}$ ), named MPCC-V3-RCMV1 and MPCC-V3-RCMV2. The former one achieves lower harmonics, whereas the latter one achieves lower switching frequency. The $\text{V}^{3}\text{s}$ are defined with basic voltage vectors that generate small CMV; hence, inherent CMV reduction can be achieved. The proposed MPCC schemes simplify the controller by redefining the cost function and control set, which reduces the computational effort significantly. Besides, the proposed MPCCs can improve the quality of current waveforms. Simulations and experiments are carried out to verify the effectiveness of the proposed control schemes.