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An efficient angle-rotation architecture, suitable for use in a digital mixer, is presented. The architecture employs a decomposition of the high-precision rotation-angle into a coarse angle and a fine angle, and employs two processing stages, coarse and fine. Only the coarse stage employs a ROM, and that ROM is extremely small. Small multipliers are shown to suffice while providing full accuracy at the system output. A systematic development of the architecture and its supporting theory and assumptions is given, along with the rationale for determining its structure. A rigorous analysis of its error sources is presented, as well as the computation of bounds for the various errors they induce at the system output. This error analysis is shown to lead to a straightforward means of designing an efficient two-stage angle-rotation unit for a digital mixer, given input/output bitwidths and performance specifications

This paper describes the architecture and IC implementation of a rectangular-to-polar coordinate converter for digital communication applications. The architecture core uses small lookup ROMs, fast multipliers, and a single angle-rotation stage. Area and latency are reduced in comparison with traditional methods. The processor, implemented in 0.25-/spl mu/m five-metal CMOS, has 14-b in-phase and quadrature channel inputs and 15-b magnitude and phase channel outputs. The phase and magnitude calculations have a maximum error of 0.00024 (0.0078% of /spl pi/) and 0.03 (1% of 2/spl radic/2), respectively. Computational latency is 19 cycles, and power dissipation is 470 mW at 2.5 V and 406 MHz (Mconversions/s).

Phase noise causes a common phase error (CPE) and inter-carrier interferences (ICI) in OFDM systems. In this paper, a novel CPE and ICI cancellation method is proposed. Comparing with compensating only the CPE, the proposed method shows significant BER improvements. These improvements are demonstrated using simulation results of an ultra-wideband system employing this CPE and ICI cancellation technique. The cost of implementation is low.

A 300-MHz quadrature direct digital frequency synthesizer/complex mixer (QDDSM) chip is presented. With a 32-bit input frequency control word, the tuning resolution is 0.07 Hz at the operating frequency of 300 MHz. The 12-bit I and Q inputs and 13-bit I and Q outputs offer a spurious-free dynamic range of 90.3 dB. The tuning latency is 13 clock cycles, which corresponds to 43 ns at 300 MHz. The tuning bandwidth (half the operating frequency) is 150 MHz. The IC is realized in 0.25-/spl mu/m TSMC CMOS technology with 4180 standard library cells and occupies a core area of 0.36 mm/sup 2/. At 300 MHz, the power dissipation is less than 400 mW. A key feature of the design is the creation of conditionally negating multipliers.

A reconfigurable angle rotator architecture is proposed and incorporated into an energy-efficient reconfigurable FFT/IFFT processor IC as its major computation component, endowing the FFT/IFFT processor with a significant scalable power dissipation feature with varying FFT size. The reconfigurability of the angle rotator is realized by dynamically allocating computation resources, which are subrotation stages in cascade. This approach tends to minimize the size of the lookup table while maintaining computation accuracy, and tends to minimize the area and power consumption while improving the overall performance.

A 400-MHz digital rectangular-to-polar coordinate converter has been implemented in 0.25-/spl mu/m CMOS. The inputs to the chip are 14-bit in-phase and quadrature channels, and the outputs are 15-bit magnitude and phase channels. The phase and magnitude calculations have a maximum error of 0.00024 and 0.03, respectively. At a maximum frequency of 406 MHz, the circuit dissipates 470 mW of power at 2.5 V.

In many communication system implementations, such as M-ary PSK and FSK modems, DMT for ADSL, as well as carrier and clock synchronization, the efficient conversion from rectangular to polar coordinates is essential. In this paper, we present a novel architecture for a circuit that computes the angle, as well as the magnitude, of a polar-form representation of a complex number, given the real and imaginary components of that number.

We present an architecture for high performance sine/cosine generation and angle rotation. Unlike CORDIC-type methods, which implement rotation using a sequence of subrotation stages, each realized, with a butterfly structure, the proposed approach implements the rotation with just two stages. We perform approximately the same number of arithmetic operations in our architecture as in CORDIC-type processors, but our architecture consolidates the operations into small array-multipliers, which can yield a smaller and faster circuit using well-known efficient multiplier implementation techniques (such as Booth encoding).

In burst-mode data transmission used in GSM and IS-136, rapid acquisition of the symbol timing and the carrier phase from the observation of a short signal-segment is essential. Feedforward timing recovery is well suited for such transmissions due to its rapid acquisition characteristics. For personal mobile communications where low complexity and low power are the major requirements, it is desirable to sample the signal at the lowest possible rate and to have the synchronizer be as simple as possible. In this paper we propose a synchronizer for initial timing and carrier-phase estimation using preambles. The synchronizer needs just two samples per symbol period and it exhibits good performance, even for signals employing small excess bandwidth. These estimations can be obtained directly from the burst detector output. We also show that the synchronizer can be implemented very efficiently.