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With the advent of 5th generation (5G) mobile communication era, higher requirements are put forward for ultra-reliable and low-latency transmission compared with 4G, especially in the field of short packet communication. In this paper, we propose a segmented cyclic redundancy check aided order statistical decoding algorithm with multiple biases (BIAS- SCRC-OSD) for short polar codes. This algorithm constructs multiple information sets by repeatedly adding bias value, and selects more effective information sets to improve the decoding performance. For further improving the decoding performance, we change the original cyclic redundancy check (CRC) into segment check. The simulation results show that a suitable bias value can significantly improve the decoding performance with a small increase in computational complexity. Compared with the original CRC-aided order statistical decoding (OSD) algorithm, the proposed algorithm has a gain of about 0.8 dB at target bit error rate (BER) 10–4 with code rate R = 0.5 and code length N = 64.

The decoding algorithms of Nonbinary low-density parity-check (NB-LDPC) codes mainly include Belief Propagation (BP), Fast Fourier Transforms (FFT) and Extended Min-Sum (EMS). Among these decoding algorithms, although EMS has the lowest decoding complexity, there is still room for improvement. Therefore, this paper proposes a new algorithm based on the EMS algorithm to further improve the decoding complexity and performance. In order to reduce complexity, an adaptive truncation rule is added to the decoding process. The adaptive truncation rule chooses the length of automatic truncation to reduce the average number of iterations. Thus, the complexity of decoding algorithm is reduced. Besides the weighting factors is added to the variable update iteration process, which effectively improves the decoding performance. The results show that the proposed algorithm has about 0.9 dB gain compared with the EMS decoding algorithm when the bit error rate (BER) is $10^{-4}$ and the Galois field GF(q) (q16).

In recent years, the demand for low latency and high reliability in industrial have been increasing rapidly. To meet these requirements, we propose a new decoding architecture of low-density parity-check convolutional codes (LDPC-CC). The proposed decoding architecture reduces the distance of the neighboring processors by using the rationale of compact pipeline decoder. At the same time, the stopping rule is employed in the process of iteration and the weighting factor is added to reduce the error propagation caused by the update of the parity-check node, thus accelerating the convergence of the decoding. The results show that the proposed algorithm has about 0.3 dB gain compared with the on-demand variable node activation (OVA) algorithm when the bit rate error (BER) is 10–4 and maximum number of iterations is 10. Meanwhile, the initial delay and storage requirement are reduced by about 50% and the average number of iterations per decoded bit is also reduced largely.