Search

An overview of quantum computers based on the annealing paradigm and manufactured by D-Wave is given. An introductory survey of this approach to quantum computing (QC), together with a snapshot of what is known about performance, is presented. Evidence-based predictions about developments in this region of the QC space are presented.

We have developed a quantum annealing processor, based on an array of tunable coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process. Implementing this type of processor at a scale of 512 qubits and 1472 programmable interqubit couplers and operating at ~ 20 mK has required attention to a number of considerations that one may ignore at the smaller scale of a few dozen or so devices. Here, we discuss some of these considerations, and the delicate balance necessary for the construction of a practical processor that respects the demanding physical requirements imposed by a quantum algorithm. In particular, we will review some of the design tradeoffs at play in the floor planning of the physical layout, driven by the desire to have an algorithmically useful set of interqubit couplers, and the simultaneous need to embed programmable control circuitry into the processor fabric. In this context, we have developed a new ultralow-power embedded superconducting digital-to-analog flux converter (DAC) used to program the processor with zero static power dissipation, optimized to achieve maximum flux storage density per unit area. The 512 single-stage, 3520 two-stage, and 512 three-stage flux DACs are controlled with an XYZ addressing scheme requiring 56 wires. Our estimate of on-chip dissipated energy for worst-case reprogramming of the whole processor is ~ 65 fJ. Several chips based on this architecture have been fabricated and operated successfully at our facility, as well as two outside facilities (see, for example, the recent reporting by Jones).

We describe a recent demonstration of a Multiply-Accumulate (MAC) unit, the core of digital signal processor that implements programmable band-pass signal filtering. This MAC unit can be clocked at 20 GHz and is capable of performing 2.5 billion MAC operations per second for 7-bit data samples and 16-bit filter coefficients arriving in bit-serial mode. The unit was designed using VHDL for functional verification and timing optimization and it was implemented in Northrop Grumman Space Technology's (NGST's) 8 kA/cm/sup 2/ J110E Niobium process. We also describe our design approach, which resulted in this successful demonstration, and discuss lessons learned, particularly the risks associated with fringe field magnetic coupling between bias and signal lines.

This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm−2, 1.25 µm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s−1, both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.

First-in, first-out (FIFO) buffers load and unload data using separate clocks that may be incoherent. We explore the application of FIFOs to circular shift registers, serial memory, and data re-clocking. We describe two different FIFO implementations in RSFQ. One employs classic handshaking using the Muller C-element. The other employs physical back-pressure based on repulsion of stored single flux quanta in a JTL. Both implementations use seven Josephson junctions, and a single bias resistor, per cell. The bias resistor can be reduced to an arbitrarily low value, thereby eliminating static power dissipation.

The Flux-1 chip is an RSFQ implementation of a small general-purpose processing engine with target clock frequency of 20 GHz and over 5000 gates (over 60 K Josephson junctions) connected in an irregular pattern. The scale of this design task forced us to re-think conventional RSFQ design methodology and implement new approaches suitable for digital systems of this level of complexity and beyond. This paper presents lessons learned from the Flux-1 effort, mostly concentrating on chip physical design. Here we discuss our approach to the circuit design and verification of individual gates, gate interconnect using passive transmission lines and use of CAD tools for design automation and verification.

This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm /spl times/10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.

Entanglement lies at the core of quantum algorithms designed to solve problems that are intractable by classical approaches. One such algorithm, quantum annealing (QA), provides a promising path to a practical quantum processor. We have built a series of scalable QA processors consisting of networks of manufactured interacting spins (qubits). Here, we use qubit tunneling spectroscopy to measure the energy eigenspectrum of two- and eight-qubit systems within one such processor, demonstrating quantum coherence in these systems. We present experimental evidence that, during a critical portion of QA, the qubits become entangled and that entanglement persists even as these systems reach equilibrium with a thermal environment. Our results provide an encouraging sign that QA is a viable technology for large-scale quantum computing., Comment: 13 pages, 8 figures, contact corresponding author for Supplementary Information

We describe the design and implementation of a single-chip microprocessor based on LTS Rapid Single-Flux-Quantum (RSFQ) technology. Two such chips are to be used in a dual-processor module, being developed by a SUNY-TRW collaboration as a spin-off of the HTMT project. Each FLUX chip represents a simple 16-bit 2-way long-instruction-word (LIW) microprocessor with a pipelined instruction memory of 30-bit instructions, decode and issue units, 8 integer ALUs interlaced with 8 registers, and input/output ports through which two FLUX chips can communicate with each other at a 7-GHz communication rate over a multi-layer MCM. The FLUX instruction set consists of /spl sim/25 instructions. High performance is reached with a scalable design featuring (1) a very high clock rate, (2) localized, regular and ultrapipelined processing in registers with very short wires, (3) instruction-level parallelism utilization with bit-level resolution of data hazards. A 16-bit implementation of FLUX processor consists of /spl sim/90,000 Josephson junctions on a /spl sim/10 mm/spl times/15 mm chip area. Our estimates show that the processor will be able to operate at clock frequencies up to 20 GHz when implemented using TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Nb-trilayer technology.

We present a design for parallel pipelined carry-lookahead Kogge-Stone 32and 64-bit integer adders with the traditional concurrent flow timing scheme, and the results of its gate-level logical simulation using a VHDL model, with parameters reduced from the physical-level simulation of RSFQ cells. The design uses only five different types of bit processing blocks and is easily scalable to any length of the operands. The multi-pulse logic representation together with interchanging logical polarity between pipeline stages is used to simplify the design of the blocks, which contain only two types of clocked RSFQ gates: an inverter and a D-flip-flop. Simulations show that in the absence of thermal fluctuations and random parameter spread the clock frequency of the adder implemented in the projected 0.8 /spl mu/m Nb-trilayer technology could be as high as 150 GHz. However, an approximate account of these factors shows that in order to achieve a 99% adder fabrication yield and a 10/sup -25/ adder error rate the maximal frequency should be reduced to 60 GHz for 1.5% Josephson junction spread and to 52 GHz for 3% spread. Adder latency is close to 260 ps for 32 bits and 320 ps for 64 bits. We plan to re-design the adders to increase their speed.

We discuss a preliminary design of a Rapid Single-Flux-Quantum (RSFQ) subsystem for general-purpose computers with petaflops-scale performance. The subsystem is being developed at Stony Brook within the framework of the Hybrid Technology MultiThreading (HTMT) project. COOL-0 design is based on 0.8-/spl mu/m RSFQ technology which enables the implementation of superconductor processing elements (SPELLs) operating at clock frequencies up to 100 GHz pipelined cryo-memory (CRAM) with 30 ps cycle time and interprocessor network (CNET) with a bandwidth of 30 Gbps per channel. The main architectural challenge is an almost 1,000-fold speed difference between the RSFQ processors and room-temperature SRAM comprising the second level of the HTMT memory hierarchy. The proposed solution to the problem is hardware support for two-level multithreading and block transfer techniques in SPELLs. Our preliminary estimates show that an RSFQ subsystem with 4 K SPELLs and a 4-Gbyte CRAM may be sufficient to achieve the performance close to 0.5 petaflops for computationally intensive program kernels. COOL-0 would occupy a physical space of about 0.5 m/sup 3/ and dissipate power as low as 250 Watts (at helium temperature). These numbers present a dramatic improvement compared to a hypothetical purely-semiconductor petaflops-scale computer.

We present a revised version of our previous RSFQ (Rapid Single Flux Quantum) microprocessor architecture and discuss approaches that we are using in the design of its functional units. In particular, the data processing pipeline built of D/sup 2/ cells, a 16-bit pipelined register block and an all-RSFQ self-reset decoder suitable for pipelined implementation are described in detail. Methods of VHDL description and verification of RSFQ circuitry are also discussed.

We are discussing a general-purpose microprocessor architecture that is suitable for implementation using the Rapid Single-Flux-Quantum (RSFQ) family of logic-memory circuits. While the microprocessor provides a functionally complete RISC instruction set with 16-bit words, a bit-serial self-timed approach makes it simple enough to be fabricated using the current Josephson junction technology. Our plans are to design, fabricate and test a completely operational prototype of this system. >

We have designed, fabricated and operated a scalable system for applying independently programmable time-independent, and limited time-dependent flux biases to control superconducting devices in an integrated circuit. Here we report on the operation of a system designed to supply 64 flux biases to devices in a circuit designed to be a unit cell for a superconducting adiabatic quantum optimization system. The system requires six digital address lines, two power lines, and a handful of global analog lines., Comment: 14 pages, 15 figures

In this paper we describe a simple and efficient ray casting engine that is suitable for the rapid exploration of irregular grids composed of tetrahedra cells, or other cell complexes where cells have been broken up into faces. In our method, in a preprocessing phase, all the cells are broken into their corresponding faces. Visibility determination is performed after all the faces have been transformed into screen space; here we compute for each pixel an ordered list of the stabbing boundary faces. The final phase is the actual ray casting, which is performed independently for each pixel, and is basically a walk in the cell complex inside each component of the stabbing ordered list. For color calculations, a simple analytical lighting model is applied to each intersection of ray and cell. Our algorithm is simple, and our implementation fast and robust.

Recent progress in the design of a superconductor digital system for high-performance computing, based on the RSFQ logic family, is briefly outlined.