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This paper presents an open source framework called Creamino . It consists of an Arduino-based cost-effective quick-setup EEG platform built with off-the-shelf components and a set of software modules that easily allow users to connect this system to Simulink or BCI-oriented tools (such as BCI2000 or OpenViBE) and set up a wide number of neuroscientific experiments. Creamino is capable of processing multiple EEG channels in real-time and operates under Windows, Linux, and Mac OS X in real-time on a standard PC. Its objective is to provide a system that can be readily fabricated and used for neurophysiological experiments and, at the same time, can serve as the basis for development of novel BCI platforms by accessing and modifying its open source hardware and software libraries. Schematics, gerber files, bill of materials, source code, software modules, demonstration videos, and instructions on how to use these modules are available free of charge for research and educational purposes online at https://github.com/ArcesUnibo/creamino . Application cases show how the system can be used for neuroscientific or BCI experiments. Thanks to its low production cost and its compatibility with open-source BCI tools, the system presented is particularly suitable for use in BCI research and educational applications.

This paper presents a different method for measuring the efficiency and the lifetime of a battery cell, that are two of the most important features for the development of hybrid and fully electric vehicles since they affect the performance of the whole system. The IEC 62660–1 is the current automotive standard procedure used to measure them, but it is not sufficient to evaluate all the performances of a cell, especially in a real scenario. The presented method allows to obtain a more accurate measure and a map of the efficiency with respect to the lifetime, reducing the number of tests and using a more realistic dynamic stress cycle. The proposed procedure has been tested on LiFePO 4 cell in order to show the difference with respect to the IEC standard.

The computing demand of many signal processing algorithms is dramatically growing because of the increasing complexity of embedded software applications. Concurrently, as process technology scales, the design effort for realizing very large scale integrated circuits and the associated costs are becoming critically high. A possible solution to address this per- formance/costs challenge is given by customizable multiprocessor system-on-chips. The approach proposed in this paper leads to the customization of multi/many processor system-on-chip at two levels of abstraction: 1) customization through application- specific hardware accelerators implemented on configurable datapath that can target three kinds of structured application- specific integrated circuit technologies: metal, via, and runtime programmable and 2) customization of the architectural para- meters of the platform. The proposed platform is equipped with a design framework that assists the user in the high-level design- space exploration of signal processing applications described using the Open Computing Language (OpenCL) language. A peculiar added value of the flow is to support the migration of OpenCL kernels and tasks into pipelined hardware accelerators described using a C-level language. The platform is able to provide an average performance of 90 GOPS on a set of reference signal processing applications, and an average computational energy efficiency of 130 GOPS/W in its metal-programmable configuration. This result shows the benefits in terms of energy efficiency of hardware customization applied to multiprocessor systems with respect to many core devices such as general- purpose graphic processing units, able to provide on average 2.5 GOPS/W for the applications under analysis.

This work deals with the solution of large non-Hermitian linear systems on desktop workstations with multiple graphics processing units (GPUs). While our implementation is motivated by the need to accelerate volume conductor modeling for bioelectrical brain imaging, the problem itself is common in scientific computing. Whenever a complex partial differential equation is numerically solved, a typically non-Hermitian sparse complex linear system needs to be solved. For problem sizes in the millions, this can take a long time even with highly optimized CPU-based solvers. Our GPU-accelerated solver outperforms an optimized OpenMP-based reference running on two quad-core CPUs by a factor of up to 31× in single precision and up to 7× in double precision, at the cost of a very modest hardware upgrade of two dual-GPU GTX 295 graphics cards. A pair of stronger Fermi GPUs (GTX 480) achieves speedups of 30× in single precision and 15× in double precision.

Dense matrix inversion is a basic procedure in many linear algebra algorithms. Any factorization-based dense matrix inversion algorithm involves the inversion of one or two triangular matrices. In this work, we present an improved implementation of a parallel triangular matrix inversion for heterogeneous multicore CPU/dual-GPU systems.

This paper describes a System on Chip implementation of a reconfigurable digital signal processor. The device is suitable for execution of a wide range of applications exploiting a balanced mix of heterogeneous reconfigurable fabrics merged together by a flexible and efficient communication infrastructure based on a 64-bit Network On Chip. The SoC combines a fine grain embedded FPGA, a mid grain configurable processor and a coarse grain reconfigurable array. An ARM processor featuring a resident operating system is the SoC supervisor, managing communication, synchronization and reconfiguration mechanisms. This computational model enables the programmer to manage the high level synchronization and global data of complex signal processing applications through the ARM processor, while allocating most critical computational kernels to the most suitable reconfigurable engines. The SoC has been fabricated in 90-nm technology, the die area being 110 mm2; it integrates 97 million transistors and has a peak power consumption of 2.5 W. In order to demonstrate the proposed computational model and the reconfigurable signal processor capabilities in a real test case, a video surveillance motion detection application was implemented in the SoC. When running this application, the device proved able to deliver 120 GOPS dissipating 1.45 W.

This paper presents a power-aware scheduling algorithm based on efficient distribution of the computing workload to the resources on heterogeneous CPU-GPU architectures. The scheduler manages the resources of several computing nodes with a view to reducing the peak power. The algorithm can be used in concert with adjustable power state software services in order to further reduce the computing cost during high demand periods. Although our study relies on GPU workloads, the approach can be extended to other heterogeneous computer architectures. The algorithm has been implemented in a real CPU-GPU heterogeneous system. Experiments prove that the approach presented reduces peak power by 10 percent compared to a system without any power-aware policy and by up to 24 percent with respect to the worst case scenario with an execution time increase in the range of 2 percent. This leads to a reduction in the system and service costs.

Diffuse optical tomography is an imaging technique, based on evaluation of how light propagates within the human head to obtain the functional information about the brain. Precision in reconstructing such an optical properties map is highly affected by the accuracy of the light propagation model implemented, which needs to take into account the presence of clear and scattering tissues. We present a numerical solver based on the radiosity-diffusion model, integrating the anatomical information provided by a structural MRI. The solver is designed to run on parallel heterogeneous platforms based on multiple GPUs and CPUs. We demonstrate how the solver provides a 7 times speed-up over an isotropic-scattered parallel Monte Carlo engine based on a radiative transport equation for a domain composed of 2 million voxels, along with a significant improvement in accuracy. The speed-up greatly increases for larger domains, allowing us to compute the light distribution of a full human head ( $\approx$ 3 million voxels) in 116 s for the platform used.

In this letter, the implementation of a system-on-chip for the documentation of road accidents is presented. Key features of the system are the implementation on a programmable architecture of a compression algorithm capable of encoding up to 20 black and white QCIF frames/s, and the computation of a digital signature performed every frame which is applied to the encoded bitstream certifying the source of the video sequence. The acquired images are then stored on a battery of on-chip flash memories that can be used to retrieve accident information to be used in legal confrontations. Having to perform in critical energy conditions (e.g., continued image acquisition for up to 10-20 s after an accident has occurred), the system was designed to minimize energy consumption at all levels. The system-on-chip has been implemented in 6/spl times/6 mm/sup 2/ on a 0.25-/spl mu/m 6-metal standard-cell CMOS technology and works at 40 MHz with a 2.5-V power supply. Performance can be decreased to 12 QCIF frames/s, 24 MHz, and 1.3-V power supply in order to achieve 30-mW power consumption.

In this study we describe an original, efficient, and innovative printed circuit board (PCB) device able to generate dielectrophoresis-based, software-controlled cages that can be moved to any place inside a microchamber. Depending on their dielectrophoretic properties, eukaryotic cells can be “entrapped” in cages and moved under software control. The main conclusion gathered from the experimental data reported is that the PCB device based on dielectrophoresis permits levitation and movement of different tumor cells at different dielectrophoresis conditions. The results presented herein are therefore the basis for experiments aimed at forced interactions or separation of eukaryotic cells using “lab-on-a-chip.” In fact, because many cages can be controlled at the same time, and two or more cages can be forced to share the same or a different location, it is possible, in principle, either to bring in contact cells of a differing histotype or to separate them. © 2003 Wiley Periodicals, Inc. Biotechnol Bioeng 82: 474–479, 2003.

This paper describes the implementation of a block-matching module with digital I/O. Algorithmic analysis demonstrates that the precision requirements can be met by a compact circuit that processes the signal in the charge domain. The required conversion between voltages and charges is achieved by MOS capacitors. As a result, it can be fabricated by any inexpensive digital CMOS technology. A test chip has been implemented in a standard CMOS 1.6 μm technology and the measured energy consumption is 1.2 nJ per block match using an 8 \times 8 pixel matrix. Simulations of the same cell in 0.35 μm and 0.25 μm CMOS technology are presented, showing the scalability of the approach.

This paper describes a VLSI array processor system designed and built for classification problems based on the k-nearest-neighbors approach. This architecture is suitable for different pattern recognition applications and is very efficient for high-dimensional databases. The architecture is scalable with the size of the recognition problem making the system effectively applicable to computational intensive application like on-line pattern recognition. A system prototype composed of a board with two processors, the software driver and a test application have been built and evaluated. For handwritten character recognition task the complete system shows a speed up of 260 times over a sequential algorithm running on a Sun SPARC20 workstation.

In this paper, a low-power, low-voltage speech processing system is presented. The system is intended to he used in remote speech recognition applications where feature extraction is performed on terminal and high-complexity recognition tasks and moved to a remote server accessed through a radio link. The proposed system is based on a CMOS feature extraction chip for speech recognition that computes 15 cepstrum parameters, each 8 ms, and dissipates 30 /spl mu/W at 0.9-V supply. Single-cell battery operation is achieved. Processing relies on a novel feature extraction algorithm using 1-bit A/D conversion of the input speech signal. The chip has been implemented as a gate array in a standard 0.5-/spl mu/m, three-metal CMOS technology. The average energy required to process a single word of the TI46 speech corpus is 10 /spl mu/J. It achieves recognition rates over 98% in isolated-word speech recognition tasks.

In this paper, a low-power, low-voltage, voice-controlled H.263 video decoding system is presented. Its power consumption makes it suitable for portable systems with limited battery resources. Video decoding of quarter-common intermediate format (QCIF) images at 25 frames per second is achieved at 1-MHz clock frequency and requires about 60 /spl mu/W at 1-V power supply, Sub-QCIF and CIF image formats are also supported. The decoder circuit is controlled by the on-chip isolated word speech recognizer. It is used to implement command-oriented and menu-based applications. The resulting system is expandable taking additional external devices under voice control. The chip integrates 650-k transistors in a 36-mm/sup 2/ area and has been implemented using a standard CMOS 0.35-/spl mu/m, five-metal technology process. The system works correctly down to 0.9 V, allowing single-cell button battery operation.

In this work we investigate techniques for embedding domain-specific spatial invariances into highly-constrained neural networks. This information is used to drastically reduce the number of weights which have to be determined during the learning phase, thus allowing us to apply artificial neural networks to problems characterized by a relatively small number of available examples. As an application of the proposed methodology, we study the problem of optical inspection of machined parts. More specifically, we have characterized the performance of a network created according to this strategy, which accepts images of parts under inspection at its input and issues a flag at its output which states whether the part is defective. The results obtained so far show that the proposed methodology provides a potentially relevant approach for the quality control of industrial parts, as it offers both accuracy and short software development time, when compared with a classifier implemented using a standard approach.

In this paper, a silicon compiler for analog fuzzy controllers is described. The layout is generated automatically, starting from global-system specifications accepted as a set of classical fuzzy rules involving fuzzy sets as well as numerical data, often available from numerical examples. The system relies on a library of basic cells designed using a CMOS n-well 0.7 /spl mu/m technology and on the use of Cadence software. Multi-inputs multi-outputs fuzzy logic-based controllers are synthesized, and the area and power requirements by any specific application are optimized. Some prototypes designed using the proposed methodology have been fabricated. For example, a two-inputs two-outputs fuzzy controller implementing a 2D rational function and a sinusoidal function requires, including the I/O circuitry, 1.9 mm/sup 2/ of silicon area, and the total power consumption is 44 mW at 5 V power supply. The maximum propagation delay, assuming a step input function, is 0.57 /spl mu/sec. The total computation time using a SUN Sparc2 Workstation is about 25 min, from specification of the expected behavior to layout.

In applications where low cost is the primary concern, analog VLSI controllers are an option. In this paper a hardware and software integrated toolkit for development of analog controllers based on fuzzy logic is presented. The system is composed of a CMOS analog circuit whose input/output relationship can be programmed to synthesize various control functions. The value of the programmable parameters can be automatically computed by the software tool, assuming that the user specifies the controller expected behavior by means of linguistic and/or numeric information. A complete example of how fuzzy linguistic and numerical methodologies can be combined with more conventional techniques to synthesize a nontrivial controller is detailed down to measured data. A final discussion clarifies the main advantages of the fuzzy analog computation when it is supported with an appropriate software layer: nontrivial solutions to problems in which accuracy is not the primary concern can be easily synthesized and integrated into very small silicon areas with small power requirements.

This paper describes the application space exploration of a heterogeneous digital signal processor with dynamic reconfiguration capabilities. The device is built around three reconfigurable engines featuring different flavours and computation granularities that make it suitable for a wide range of signal processing application domains such as video coding, image processing, telecommunications, and cryptography. Performance of signal processing applications is evaluated from measurements performed on a CMOS 90 nm prototype. In order to characterize the application space of the processor, performance is compared with state-of-the-art devices, taking programmability, computational capabilities, and energy efficiency as the main metrics. The device exploits performance and energy efficiency significantly more than general purpose processors, while still maintaining a user-friendly programming approach that mainly relies on software-oriented languages. The device is able to achieve 1.2 to 15 GOPS with an energy efficiency from 2 to 50 GOPS/W when running the selected applications.

A new statistical classifier for handwritten character recognition is presented. After a standard preprocessing phase for image binarization and normalization, a distance transform is applied to the normalized image, converting a black and white (B/W) into a gray scale picture. The latter is used as feature space for a k -Nearest-Neighbor classifier, based on a dissimilarity measure which generalizes the use of the distance transform itself. The classifier has been implemented on a massively-parallel processor, Connection Machine CM-2. Classification results of digits extracted from the U.S. Post Office ZIP code database and the upper-case letters of the NIST Test Data 1 are provided. The system has an accuracy of 96.73% on the digits and 94.51% on the upper-case letters when no rejection is allowed and an accuracy of 98.96%, on the digits and 98.72% on the upper-case letters at 1% error rate.

The two-dimensional massively parallel electromagnetic simulation program TEMPEST has been generalized to extend its applicability to many of the difficult problems in photolithography, metrology, and alignment. TEMPEST, which has been made available on the NCSA and other computing centers, combines together techniques for analysis of the transverse electric (TE) and the transverse magnetic (TM) polarizations, oblique incidence, highly dispersive materials, and a technique for synthesis of partially coherent optical images. The solution is based on the time-domain finite-difference method, but exploits the power of massively parallel computer architectures. Equations suitable for massively parallel implementation are given for oblique incidence, both polarizations and dispersive materials. Computer time per iteration cycle is constant irrespective of the polarization and angle of incidence. However, the total simulation time for convergence was found to be dominated by physical scattering phenomena. Convergence for the TM polarization is 1.5 times slower than the TE polarization because of edge currents, and oblique incidence is 2 times slower than normal incidence owing to artificial reflection from the domain boundaries. A typical simulation time is three to five minutes with 256 k (1 k=1024) simulation nodes on a CM-2 with 8 k processors. The effectiveness of the program for photolithographic applications is demonstrated by considering the effects of subtle changes in phase-shifting mask topography on the optical images. >

We present a generalized self‐scattering method for generating carrier free flight times in Monte Carlo simulation. Compared to traditional approaches, the added flexibility of this approach results in fewer fictitious scatterings, which is especially appealing for load balance and efficiency when a SIMD parallel computer is used. Speedups from 19% to 69% over an optimized variable‐Γ approach are shown for an implementation on the Connection Machine CM‐2. The performance sensitivities to applied fields and grid spacings are also presented. The conversion of existing variable‐Γ software to this new approach requires only a few changes.

Electrical impedance tomography (EIT) is an imaging technology based on impedance measurements. To retrieve meaningful insights from these measurements, EIT relies on detailed knowledge of the underlying electrical properties of the body. This is obtained from numerical models of current flows therein. The nonhomogeneous and anisotropic electric properties of human tissues make accurate modeling and simulation very challenging, leading to a tradeoff between physical accuracy and technical feasibility, which at present severely limits the capabilities of EIT. This work presents a complete algorithmic flow for an accurate EIT modeling environment featuring high anatomical fidelity with a spatial resolution equal to that provided by an MRI and a novel realistic complete electrode model implementation. At the same time, we demonstrate that current graphics processing unit (GPU)-based platforms provide enough computational power that a domain discretized with five million voxels can be numerically modeled in about 30 s.

This contribution presents new algorithms for the automatic simplified computation of symbolic transfer functions of linear circuits. The problem of symbolic simplification of transfer functions is defined and a set of algorithms able to cope with this problem and the simplified computation of poles and zeroes is developed and discussed. Results are reported with examples of circuits analyzed by our algorithms, showing good accuracy in their approximation, when compared to the corresponding SPICE simulations. Our technique merges the simplification procedure and the evaluation of the transfer functions, thus achieving significant improvements in terms of CPU time, compared with direct evaluation of the functions themselves.

International audience; This paper describes the RTL-to-Layout implementation of the PACT XPP-III Coarse-Grained Reconfigurable Architecture (CGRA). The implementation activity was strictly based on a hierarchical approach in order to exploit performance optimization at all levels, as well as guarantee maximum scalability and provide a portfolio of IP-blocks that could be reused to build different configurations and embodiments of the same CGRA template. The final result can be seamlessly introduced in any SoC design flow as embedded accelerator. It is designed in STMicroelectronics 90nm GP technology, occupies 42.5 mm2, delivers 13 16-bit GOPS (0.8 GOPS/mW, 10 MOPS/mW) and has a measured max frequency of 150 MHZ, requiring a measured 13 mW/MHz dynamic power, 93 mW static. A silicon prototype was also produced embedding XPP-III in a complex system-on-chip including an ARM processor as system controller as well as different ASIC blocks.

Printed circuit board (PCB) technology can be used for producing lab-on-a-chip (LOAC) devices. PCBs are characterized by low production costs and large-scale development, both essential elements in the frame of disposable applications. LOAC platforms have been employed not only for diagnostic and/or analytical purposes, but also for identification and isolation of eukaryotic cells, including cancer and stem cells. Accordingly, the compatibility of the employed materials with the biological system under analysis is critical for the development of LOAC devices to be proposed for efficient and safe cell isolation. In this study, we analyzed the in-vitro compatibility of a large set of materials and surface treatments used for LOAC development and evaluation with quasi-standard PCB processes. Biocompatibility was analyzed on hippocampal primary cells (a model of attached cell cultures), in comparison with the reference K562 cell line (a model of cells growing in suspension). We demonstrate here that some of the materials under study alter survival, organization, morphology and adhesion capacity of hippocampal cells, and inhibit growth and differentiation of K562 cells. Nonetheless, a subset of the materials tested did not negatively affect these functions, thus demonstrating that PCB technology, with some limitations, is suitable for the realization of LOAC devices well compatible at least with these preparations.

Dense matrix inversion is a basic procedure in many linear algebra algorithms. A computationally arduous step in most dense matrix inversion methods is the inversion of triangular matrices as produced by factorization methods such as LU decomposition. In this paper, we demonstrate how triangular matrix inversion (TMI) can be accelerated considerably by using commercial Graphics Processing Units (GPU) in a standard PC. Our implementation is based on a divide and conquer type recursive TMI algorithm, efficiently adapted to the GPU architecture. Our implementation obtains a speedup of 34x versus a CPU-based LAPACK reference routine, and runs at up to 54 gigaflops/s on a GTX 280 in double precision. Limitations of the algorithm are discussed, and strategies to cope with them are introduced. In addition, we show how inversion of an L- and U-matrix can be performed concurrently on a GTX 295 based dual-GPU system at up to 90 gigaflops/s.

Dielectrophoresis (DEP)-based lab-on-a-chip devices represent a very appealing approach for cell manipulation and will enable laboratory testing to move from laboratories into nonlaboratory settings. DEP-based lab-on-a-chip platforms involve the miniaturization of sev- eral complex chemical and physical procedures in a single microchip-based device, allowing the identification and isolation of cell populations or single cells, separation of cells exhibiting dif- ferent DEP properties, isolation of infected from uninfected cells, and viable from nonviable cells. In addition, DEP-arrays allow cellomics procedures based on the parallel manipulation of thousands of cells. Arrayed lab-on-a-chip platforms are also suitable to study cell–cell interac- tions and cell targeting with programmed numbers of microspheres.

A 3D interconnection scheme based on capacitive coupling for high speed chip to chip communication has been implemented in a 0.13 mum CMOS process. This paper provides detailed design example for both synchronous and asynchronous transmitter and receiver circuits. The first approach shows with electrodes 15 times 15 mum2 a wide range of operating frequency up to 900 MHz with an energy consumption of 41fJ/bit. In the asynchronous scheme we demonstrate with electrodes 8 times 8 mum2 a vertical propagation of clock at 1.7 GHz and a propagation delay of 420 ps for general purpose signal with energy consumption of 80 f J/bit. Functionality and performance have been demonstrated by using both die-level and wafer-level assembly flows and BER measurements show the reliability of these AC interconnections with no error on more than 1013 bits transmitted.

Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. This paper presents the design of AES/Rijndael on a dynamically reconfigurable architecture. A performance improvement of three order of magnitude was shown compared to the reference code and up to 24times speed-up figure wrt fast C implementations over a RISC processor. A maximum throughput of 546 Mbit/sec is achieved. Compared to prior art, a better energy efficiency with respect to the other programmable solutions was shown, obtaining up to 3 Mbit/sec/mW

Monitoring harsh environments such as underwater scenarios or aircraft external surfaces pertains to important applications like assisted navigation and tactical surveillance; nevertheless, it poses additional challenges compared with standard applications. At Transducers2005 we presented a wired addressing architecture of distributed sensors for monitoring real-time in-situ pressure variations in underwater environment that faces the above-mentioned issues. This architecture consists in a double array of identical and interconnected smart nodes monitoring a matrix of passive sensors. In this paper, we present an analysis of the delay model related to the presented architecture and a calculation of the overall frame-rate of the system as a function of the geometrical topology of the arrays. The topology of the network, i.e. the length of each bus and the number of nodes, can be chosen according to the application, and directly affects the global capacitive load on the serial lines. Each serial line can be schematized with a distributed RC model for the flat cable plus a lumped capacitance for each smart node. Then, a 3rd-order pi-segmented model of O'Brien-Savarino is calculated for a 16-block line with block length equal to 0.3 m. Thanks to that, the global time per iteration is calculated on each bus as well as the scanning time of the whole matrix and the frame rate for the system as a function of sensor distribution and of the aspect ratio of the matrix. This model can be employed to identify the optimal arrangement for the sensor matrix and smart node arrays

The skin care retains a great importance for both aesthetics and health. Nowadays, many different approaches are known to quantify the skin health status by analyzing the skin appearance. However, most of these methods are still grounded on surface replicas, or on the use of devices that are not suitable for a routine approach. Also not all the methods are designed to achieve results in an automatic manner. The work presented here describes a method to extract an age-related feature from high resolution capacitive map of the human skin achieved by a portable device. Skin surface samples of 87 subjects have been analyzed in vivo and automatically through using wavelet decomposition. After that samples have been enhanced, we devised a feature, which correspond to the energy of the wavelet coefficients at the finest scale. Experiments prove that the feature we extracted is linearly related to skin ageing.

Quantitative evaluation of the changes in skin topographic structures are of great importance in the dermocosmetic field to assess subjects response to medical or cosmetic treatments. Although many devices and methods are known to measure these changes, they are not suitable for a routine approach and most of them are invasive. Moreover, it has always been difficult to give a measure of the skin health status as well as of the human aging process by simply analyzing the skin surface appearance. This work describes how a portable capacitive device could be utilized to achieve measurements of skin ageing in vivo and routinely. The capacitive images give a high resolution representation of the skin micro-relief, both in terms of skin surface tissue and wrinkles. In a previous work we dealt with the former; here we have addressed the latter. The algorithm we have developed allowed us to extract two original features from wrinkles: the first is based on photometric properties while the second has been achieved through the multiresolution analysis of the wavelet transform. Accurate experiments accomplished on 87 subjects show how the features we conceived are related to skin ageing.

In dermatology and in cosmetic science, the detailed analysis of the skin surface is still a key requirement to evaluate the effectiveness of medical or cosmetic treatments. Nowadays, the assessment of skin surface topographic structures such as wrinkles or micro-relief 3D profile is mainly obtained by profilometric analysis. Even though such an analysis gives a high level of detail, it is not suitable for in vivo studies since it requires the use of silicone cast replica of the skin. However, in the last few years a portable capacitive device has been proposed for in vivo skin topography characterization. This work presents the method we have developed to assess the capability of the capacitive device to provide reliable absolute measures of the skin surface structures. Extensive experiments carried out by comparing the measures achieved by means of the capacitive device and an optical profilometer allow us to validate our method.

This paper introduces a novel heterogeneous shared memory multiprocessor architecture based on a reconfigurable processor and a standard RISC processor. The work aims at increasing further the computational density of a reconfigurable device by the integration of the reconfigurable hardware into a heterogeneous multi-core architecture. Though a RISC processor has a lower inner computational density than a reconfigurable processor, this work demonstrates that coupling a reconfigurable core to a RISC core leads to a computational density increase by a factor of up to 1.7times on signal processing applications. Moreover, this approach also achieves up to 37% energy savings on the same applications. The multi-core SoC architecture was implemented in 0.13mum technology, achieving a 166MHz clock frequency with an average 340mW power consumption

The skin care reveals of great importance for matters of both aesthetics and health. Often, the skin appearance gives us information about the skin health status as well as hints at the age of a person. However, it has always been difficult to give a measure of the skin health status as well as of the human aging process by simply analyzing the skin surface appearance. This could help dermatologists as well as cosmetic scientists to evaluate the effectiveness of medical or cosmetic treatments. So far, no in vivo measurements regarding skin topography features have been achieved to evaluate routinely skin ageing by a portable device. This work describes how a portable capacitive device could be utilized to achieve measures of skin ageing in vivo and routinely. The capacitive images give a high resolution representation of skin topography, in terms of wrinkles and cells: in this work we have addressed the former. Accurate experiments accomplished on 90 subjects show how the feature we conceived is linearly related to skin ageing.

Reconfigurable computing can face many of the current embedded systems design issues, providing a high degree of flexibility and increasing energy efficiency of computation. This paper introduces the architecture of a system on chip for signal processing applications, including an XiRisc reconfigurable processor as the main computational core. This RISC processor features an extensible instruction set, obtained through dynamic reconfiguration of a programmable gate-array embedded as a processor datapath function unit. A prototype chip has been implemented in 0.13 /spl mu/m CMOS technology. The SoC operates at 166 MHz clock speed and the test of several DSP algorithms showed speed-ups ranging from 5/spl times/ to 80/spl times/ with 65%-95% energy savings. As proof of the architectural improvement, energy and area computational efficiency has grown by a factor ranging from 3/spl times/ to 35/spl times/.

This paper describes a new architecture for embedded reconfigurable computing, based on a very-long instruction word (VLIW) processor enhanced with an additional run-time configurable datapath. The reconfigurable unit is tightly coupled with the processor, featuring an application-specific instruction-set extension. Mapping computation intensive algorithmic portions on the reconfigurable unit allows a more efficient elaboration, thus leading to an improvement in both timing performance and power consumption. A test chip has been implemented in a standard 0.18-/spl mu/m CMOS technology. The test of a signal processing algorithmic benchmark showed speedups ranging from 4.3/spl times/ to 13.5/spl times/ and energy consumption reduced up to 92%.

A standard-CMOS pointing device for portable applications, such as palmtop and credit-card size computers, is based on fingerprint-motion detection. The device behaves much the same as a track-ball, but it does not require mechanical moving parts and can be fabricated in a smaller package. Pointing devices based on image motion estimation were previously reported. In contrast to these devices, this implementation produces the moving image by direct chip-finger contact.

Flexibility, high computing power and low energy consumption are strong guidelines when designing new generation embedded processors. Traditional architectures are no longer suitable to provide a good compromise among these contradictory implementation requirements. In this paper we present a new reconfigurable processor that tightly couples a VLIW architecture with a configurable unit implementing an additional configurable pipeline. A software development environment is also introduced providing a user-friendly tool for application development and performance simulation. Finally, we show that the HW/SW reconfigurable platform proposed achieves dramatic improvement in both speed and energy consumption on signal processing computation kernels.

The authors describe the design and implementation of an application-specific digital architecture aimed at the solution in real time of the "K nearest neighbors" algorithm for classification problems, whose computational weight is very high. The system described here is an array-processor architecture in which the data base is split among several units that at the same time apply the same operations to different data stored in local memories. The sustained memory bandwidth of a system featuring 8 units is 2560 Mb/s and it provides a speed-up of 500 times over the software algorithm running on a SUN Sparc2 workstation. >

This paper describes the design and implementation of an application-specific digital architecture aimed at performing the mining of fuzzy database. The system described is an array-processor architecture in which the database is split among several units that at the same time apply the same operations to different data stored in local memories. A chip set implementing the architecture has been built using a semicustom approach and it is fully functional. The sustained memory bandwidth of a system featuring 8 units is 2560 Mbit/sec and it provides a speed-up of 500 times over the software algorithm running on a SUN Sparc2 workstation. >

In this paper we study the cost structure of a software system for the visual classification of industrial parts. We investigate two different development methodologies and compare them using a suitable cost function. The first approach aims to the development of a piece of software fully tailored to the specific problem, while the second one exploits the capabilities of adaptive signal processing techniques to reduce the software production test. >

In this paper, the virtual emulation problem is addressed. We give sufficient conditions for a digital system to be emulable. Moreover, we present sufficient conditions under which system emulation can degenerate from an event-driven to a faster cycle-based simulation. The OMI (Open Model Interface), an emerging standard modeling interface for digital systems, has been considered to develop an emulation system that is usable in every OMI-compliant simulation environment.

A low-power feature extraction chip computing cepstral coefficients from linear predictive analysis on one-bit quantized speech signals is presented and its VLSI implementation is evaluated. An isolated-word small-vocabulary speech recognizer based on these features has been developed. Its recognition accuracy is within 2% below a system based on standard linear predictive cepstral features. The power consumption of the feature extractor chip is 30 /spl mu/W at 0.9 V.

This paper presents the board-level prototype implementation of a complete speech recognition system. The recognition system is based on a chip set still under development and, in its final implementation, it will perform real-time isolated-word recognition of up to 1000 word templates. In this paper we show that virtual emulation is an effective approach to high-level system prototyping and verification and achieves a smooth evolution of the prototype to its final implementation. Methodology guidelines are given to handle designs having subsystems whose clock speeds cannot be slowed down at the virtual emulation speed. The case of a real-time speech acquisition user interface is presented. In addition, speed-up techniques providing a threefold improvement in emulation time are discussed. The board-level prototype system has been designed, built and tested in 2 man/months.

A low-power architecture for 2D-DCT is presented. It has been designed for portable H.261-compliant video-telephone applications, but most of the results and considerations apply to MPEG systems too. The presence of quantization in the coding process has been exploited, adapting the precision of DCT calculations to the quantization noise level. The proposed architecture has the capability of dynamically controlling power consumption by reducing the precision to the minimum required level and turning off sub-systems when they are not necessary for the computation. Compared with a standard implementation, power consumption is reduced by a factor between 7 and 10, without appreciable degradation of the transmission quality.

Low power digital techniques to reduce power dissipation during write operations are implemented in 3V-only, 1M cells, NOR-flash memory. The test chip is fabricated in 0.5 /spl mu/m, 3-metal, triple-cell CMOS technology. Measurement results show that these methods combined with conventional low current programming algorithms allow a reduction in power consumption of 40% with a 20% reduction of overhead in total chip area.

Microelectronics holds the promise to bring to biology the advantages of miniaturization for carrying out highly automated experiments, under software control, with increased speed and low cost. This paper describes an essential building block for this scenario: a method for the stable levitation and independent motion of microorganisms in a liquid and their precise displacement by means of an electronic programmable device.

The design flow and implementation of a system-on-chip for the documentation of road accidents is presented. Key features of the system are the implementation, on a programmable architecture, of a compression algorithm capable of encoding up to 15 black & white QCIF frames/s, and the computation of a digital signature performed every frame which is applied to the encoded bitstream certifying the source of the video sequence. The system has been implemented in 6/spl times/6 mm/sup 2/ on a 0.25 /spl mu/m, 6-metal standard-cell CMOS technology and works at 40 MHz, 2.5 V power supply. The adoption of IP reusable cores has allowed the system to be completed in 1 man-year time from idea to physical implementation.