Search

The main purpose of the proposed system is to design a low-cost universal PV battery charger for electric vehicle application. The proposed system is integrated with a slope-compensated current controller which controls the charging current that corresponds to maximum power point of the PV module. As an interface converter, the proposed system consists of a buck converter to control the flow of the charging current and to find out the reference current Iref from the PV array at MPP. The battery control circuit is implemented by measuring the state of charge (SOC) of the battery, and an LCD display has been used to monitor the battery parameters. This proposed system acts as a smart and efficient PV battery charger for e-vehicles.

Biological hands work by picking up signals from muscle and is controlled by tensing the same muscle. This paper proposes a lightweight bionic hand built based on this concept and considering the high performance and low-cost factors. Layer manufacturing (LM) also known as 3D printing is trending manufacturing set up considering zero material waste and generating ideas into 3D geometrical model. The layers are produced one by one by lowering the material deposition platform and built as per a 3D CAD model. Layered manufacturing process is open to handle wide variety of materials such as polymers, metals, composites. In this research study, a lightweight robotic hand has been modeled using 3D CAD software and the CAD model is generated using a 3D printer. The hand is then interfaced with Arduino, where the sensors and actuators are then programmed for the individual finger movement. The individual performance of each finger is analyzed for both linear and rotational movement by getting signals from the flex sensor. Furthermore, the load carrying capacity of the hand is also analyzed. The force required to pick or lift the object by using this artificial arm is determined which is solely determined by the capacity of the servomotor being used.

In this article, we derive a simple and accurate expression for the change in timing yield due to a change in the gate delay distribution. It is based on analytical bounds that we have derived for the moments of the circuit and path delay. Based on this, we propose computationally efficient algorithms for (1) discrete gate sizing and (2) simultaneous gate sizing and threshold voltage ( V T ) assignment so that the circuit meets a timing yield specification under parameter variations. The use of this analytical yield gradient within a gradient-based timing yield optimization algorithm results in a significant improvement in the runtime as compared to the numerical method, while achieving the same final yield. It also allows us to explore a larger search space in each iteration more efficiently, which is required in the case of simultaneous resizing and V T assignment. We also propose heuristics for resizing/changing the V T of multiple gates in each iteration. This makes it possible to optimize the timing yield for large circuits. Results on ITC ’99 benchmarks show that the proposed multinode resizing algorithm results in a significant improvement in the runtime with a marginal average area penalty and no cost to the final yield achieved.

Statistical timing yield optimization algorithms require computation of yield-gradient for gate resizing in every iteration. Numerical yield-gradients account for the effects of fan-in and fan-out gates, but are computationally expensive. In this paper, we formulate a more accurate analytical expression for the yield-gradient (termed effective yield-gradient) that includes these effects. Based on the statistical properties of the path delay variations, we derive a simplified expression for the effective yield gradient that is accurate and results in an improvement in the run-time. Using these simplified expressions, we also propose an algorithm for resizing multiple gates in an iteration. Results on ITC99 and ISCAS85 benchmarks show that the proposed multi-node resizing algorithm results in 83% improvement in the runtime with an average area penalty of 3% and no cost to the final yield achieved.

This paper focuses on power loss analysis of non-isolated hard switching boost converter and quasi resonant ZVS (zero voltage switching) soft switching boost converter for various switching frequency in Power Conditioning System (PCS). Efficiency comparison and power losses of passive components are calculated for various switching frequency. The design and performance of the system is verified through simulation using PSPICE software.

The statistical nature of gate delays in current day technologies necessitates the use of measures, such as path criticality and node/edge criticality for timing optimization. Node criticalities are typically computed using the complementary path delay. An alternative approach to compute the criticality using the circuit delay has been recently proposed. In this paper, we discuss in detail, the use of circuit delay to compute node criticalities and show that the criticality thus found is not equal to the conventional measure found using complementary path delay. However, there is a monotonic relationship between them and the two measures can be used interchangeably. We derive new bounds for the global criticality and propose a pruning algorithm based on these bounds to improve the accuracy and speed of computation. The use of this pruning technique results in a significant speedup in criticality computations. We obtain an order of magnitude average speedup for ISCAS benchmarks.

Due to the statistical nature of gate delays in current day technologies, measures such as path criticality and node/edge criticality are required for timing optimization. Node criticalities are usually computed using the complementary path delay. In order to speed up computations, it has been recently proposed that the circuit delay be used instead. In this paper, we show that there is a monotonic relationship between the node criticalities computed using the circuit delay and the complementary delay. They are not equal, but they can be used interchangeably. We discuss the sources of error in this computation and propose methods for more accurate computations. We also introduce a measure that is very easy to compute and is an approximate indicator of criticality. Since it is easy to compute, it can also be used effectively for pruning the number of edges involved in criticality computations thus improving the speed of criticality computations. The speedup obtained can be as large as an order of magnitude for some of larger circuits in the ISCAS benchmarks.

This paper deals with Four Quadrant Operation of Direct Torque Control (DTC) - Space Vector Pulse Width Modulation (SVPWM) based 3-phase Induction Motor Drive using MATLAB and its toolbox SIMULINK. The Classical Direct Torque Control of VSI fed Induction Motor is implemented with the help of Hysteresis Band (HB) controllers (one for flux control and other for torque control), a voltage source inverter and a switching table. Classical DTC has the disadvantages like variable & high switching frequency and high torque and current ripples in steady state. To overcome these difficulties SVPWM is employed in the proposed model. With aid of the developed model, the steady and transient-state characteristics of current, speed and torque of three phase induction motor can be effectively examined and analyzed. This proposed model can be projected as a trouble-free design tool for the development of three phase induction motor drives.

In this paper, a novel approach for phoneme classification using binary feature vector and correlation based classifier is proposed. The input speech segmentation is carried out using the Average Level Crossing Rate (ALCR) information. A 513-point binary feature vector is generated for each of the phoneme segment detected by ALCR boundaries. The phoneme recognition is based on the uniqueness of the frequency content of each of the phoneme. Instead of using a Hidden Markov Model, Artificial Neural Network or Support Vector Machine based classifier, a simple correlation classifier using the correlation between feature vectors and the set of feature vectors generated with training data is employed. The proposed approach is simpler and requires lesser computational resources when compared with other pattern classification techniques. The performance of proposed phoneme recognition system has been evaluated using real-time speech input and the recognition performance of the proposed phoneme recognition system is satisfactory.