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Nowadays, security and confidentiality are considered as important aspects throughout the growth of computerized systems, information technology, and internet communication. The cryptographic algorithms are used to improve the security against various threats/attacks (e.g., differential attacks and statistical attacks). In this research, the modified PRESENT architecture is proposed to improve the security against unauthorized users while minimizing the hardware utilization. The PRESENT architecture is modified by proposing three key strategies; (1) three Stage Reversible Logic Key Generation (3S-RLKG) is developed to generate the optimal key value using three different gates such as Feynman gate, DFG gate and Toffoli gate, (2) Modified Key Scheduling (MKS) and Bit Reversible Function (BRF) is additionally used in the PRESENT architecture to increase the confusion property and (3) mitigation of the Read-Only Memory (ROM) to store the intermediate values in the Field Programmable Gate Array (FPGA) processor. Therefore, the higher confusion property leads to an increase in the security against the unauthorized users. The performance of 3S-RLKG-PRESENT architecture is evaluated by means of the number of slice registers, flip flops, number of Look Up Table (LUT), number of logical elements, slices and bonded input/output block (IOB). Moreover, the 3S-RLKG-PRESENT architecture is also analyzed in the Spartan 6 XC6SLX9 -2 TQG144 FPGA hardware. The 3S-RLKG-PRESENT architecture is compared with different existing PRESENT architectures namely Maximum Distance Separable (MDS) based PRESENT, PRESENT, PRESENT with X Compactor, PRESENT- Round Key Generation (RKG), PRESENT- Storage Mode (SM) and Pseudo Random Bit Generator (PRBG). The 3S-RLKG-PRESENT designed in the Spartan 6 consumes 131 LUTs, 70 flip flops and 48 slices which are less when compared to the PRESENT-RKG.

Quantum circuits for performing an arithmetic operation are necessary for the implementation of quantum computing peripherals. An effective quantum circuit can be developed using a minimum amount of Clifford + T gates, as the implementation of Clifford + T quantum gates is more expensive than the other quantum gates. A quantum full adder (QFA) circuit for quantum computing hardware is proposed in this work. The proposed QFA circuit is optimized for T-count using a single CCNOT (Toffoli) gate. This work also focuses on implementing a quantum integer multiplication circuit using the proposed QFA to achieve better T-count savings than the existing counterparts.

We present a new algorithm for synthesis of reversible circuits for arbitrary n-bit bijective functions. This algorithm uses generalized Toffoli gates, which include positive and negative controls. Our algorithm is divided into two parts. First, we use partially controlled gen- eralized Toffoli gates, progressively increasing the number of controls. Second, exploring the properties of the representation of permutations in disjoint cycles, we apply generalized Toffoli gates with controls on all lines except for the target line. Therefore, new in the method is the fact that the obtained circuits use first low cost gates and consider increasing costs towards the end of the synthesis. In addition, we employ two bidirectional synthesis strategies to improve the gate count, which is the metric used to compare the results obtained by our algorithm with the results presented in the literature. Accordingly, our experimental results consider all 3-bit bijective functions and twenty widely used benchmark functions. The results obtained by our synthesis algorithm are competitive when compared with the best results known in the literature, considering as a complexity metric just the number of gates, as done by alternative best heuristics found in the literature. For example, for all 3-bit bijective functions using generalized Toffoli gates library, we obtained the best so far average count of 5.23.

In recent years, reversible circuits have attracted the attention of many researchers. Their applications include the design of low-power digital circuits, the design of computational circuits in quantum computers and DNA-based calculations. In this paper, an effective 5 × 5 reversible block, called new block (NB), is first proposed, and then, using the proposed reversible block, a novel reversible T flip-flop is designed. Moreover, we have used Miller synthesis method for calculating the optimal quantum cost of the proposed block. Finally, using the proposed T flip-flop, Feynman gate (FG), Fredkin gate (FRG), Reversible Multiplexer1 (RMUX1) and Modified Toffoli gate (MTG), two reversible synchronous counters including up/down and BCD are suggested. The comparison results show that the proposed up/down counters are superior to the previous designs in terms of parameters such as gate count, constant input, garbage output, quantum cost, and delay.

In the last decade, the synthesis of reversible logic circuits has become a trending topic because of its future necessity and importance. Many methods have been studied and proposed, for instance, transformation-based, search-based, cycle-based, ESOP-based and BDD-based methods. Each of them has its limitation related to time processing, ancilla and garbage line, quantum cost. This study develops an algorithm that could synthesize quantum circuits based on mixed-polarity Toffoli gate and a variant of binary decision diagram (BDD) called reduced-ordered-complemented edge-bdd (ROCBDD). It is an optimized method of BDD to reduce nodes in the representation of Boolean functions, which leads to adding more lines and quantum gates in the reversible circuit. First, the differences between synthesis using ROCBDD, the traditional BDD and others methods are introduced. Then, we define a new structure consisting of mixed-polarity Toffoli gates relied on nodes of ROCBDD. An efficient algorithm to match BDD representation to the reversible logic circuit is also mentioned. Finally, the experimental results show that our algorithm has better synthesizing costs than previous BDD-based methods.

Heat dissipation is one of the major problems in the construction of electronic devices. Reversible computing is one of the emerging computing paradigms to overcome heat dissipation problem. One of the nanoscale devices that has low power consumption and can be used to construct digital logic components is quantum-dot cellular automata (QCA). In this paper, the benefits of reversible computing of QCA will be used to propose QCA designs for two main reversible gates, the CNOT and the TOFFOLI gates. The proposed CNOT gate has been used to design QCA for double CNOT gate to show its reversibility, and QCA design for the SWAP circuit that contains 3 CNOT gates. The suggested TOFFOLI gate is utilized to construct QCA for double TOFFOLI gate and a reversible circuit which consists of several reversible gates. The suggested QCA designs for double CNOT, double TOFFOLI and reversible circuits such as SWAP circuit have been proposed by adding cells with certain clocks to the wires that connects the proposed gates. The proposed QCA designs show better cell count, area used in the construction, number of majority gate, wire crossover, and/or clock cycle delay when compared with relevant designs in literature.

Quantum-dot cellular automata (QCA) are the potential alternative to complementary metal–oxide–semiconductor-based technology. Ideally, zero power dissipation can be achieved with the help of reversible computing. In this study, a novel design of a reversible priority encoder based on QCA is proposed. The basic building blocks for the design are Toffoli and BJN gates. The proposed design is verified by the QCA designer simulator. The performance analysis of the reversible priority encoder is performed based on the simulation results. The proposed encoder not only overcomes the problem of the messy code but also declines the amount of heat energy dissipation through reversible logic. The proposed reversible circuit could be a major component in future wireless communication because reversible logic accounts for zero loss of information. The estimation of power consumption by proposed QCA circuits is explored that implies QCA can be an ideal platform to implement reversible circuits. The relationship with recently proposed work is also discussed.

Every quantum algorithm is represented by set of quantum circuits. Any optimization scheme for a quantum algorithm and quantum computation is very important especially in the arena of quantum computation with limited number of qubit resources. Major obstacle to this goal is the large number of elemental quantum gates to build even small quantum circuits. Here, we propose and demonstrate a general technique that significantly reduces the number of elemental gates to build quantum circuits. This is impactful for the design of quantum circuits, and we show below this could reduce the number of gates by 60% and 46% for the four- and five-qubit Toffoli gates, two key quantum circuits, respectively, as compared with simplest known decomposition. Reduced circuit complexity often goes hand-in-hand with higher efficiency and bandwidth. The quantum circuit optimization technique proposed in this work would provide a significant step forward in the optimization of quantum circuits and quantum algorithms, and has the potential for wider application in quantum computation.

Heuristic algorithms play a significant role in synthesize and optimization of digital circuits based on reversible logic yet suffer with multiple disadvantages for multiqubit functions like scalability, run time and memory space. Synthesis of reversible logic circuit ends up with trade off between number of gates, quantum cost, ancillary inputs and garbage outputs. Research on optimization of quantum cost seems intractable. Therefore post synthesis optimization needs to be done for reduction of quantum cost. Many researchers have proposed exact synthesis approaches in reversible logic but focussed on reduction of number of gates yet quantum cost remains undefined. The main goal of this paper is to propose improved Ant Colony Optimization (ACO) algorithm for quantum cost reduction. The research efforts reported in this paper represent a significant contribution towards synthesis and optimization of high complexity reversible function via swarm intelligence based approach. The improved ACO algorithm provides low quantum cost based toffoli synthesis of reversible logic function without long computation overhead.

Investigations in reversible computation have been one of the notable dimensions among the emerging research domains. Reversible circuits promise near-zero heat dissipation resulting in a considerable amount of literary proposals. This article proposes a reversible synchronous decimal counter using Toffoli and Fredkin gates. Decimal counter forms an important Boolean specification as they are used for clock generators, frequency dividers, clock division, integrated oscillation, etc. Although literature witnesses exhaustive research in reversible mod-2/4/8/16 counters, there is a void in the domain of reversible decimal counters. We propose three designs D1, D2, and D3. Design D1 and D2 are synchronous decimal up and down counters, respectively, using Toffoli Netlist. Design D3 is the integration of designs D1 and D2 using the Fredkin Gate array. The proposed designs have been checked using a state-of-the-art optimization algorithm in literature and the results reflect our design to be best optimized. Peer analysis reflects a summary of existing literary proposals exhibiting the uniqueness of the proposed designs.

We advocate for a fundamentally different way to perform quantum computation by using three-level qutrits instead of qubits. In particular, we substantially reduce the resource requirements of quantum computations by exploiting a third state for temporary variables (ancilla) in quantum circuits. Past work with qutrits has demonstrated only constant factor improvements, owing to the log2(3) binary-to-ternary compression factor. We present a novel technique using qutrits to achieve a logarithmic runtime decomposition of the Generalized Toffoli gate using no ancilla---an exponential improvement over the best qubit-only equivalent. Our approach features a 70x improvement in total two-qudit gate count over the qubit-only decomposition. This results in improvements for important algorithms for arithmetic and QRAM. Simulation results under realistic noise models indicate over 90% mean reliability (fidelity) for our circuit, versus under 30% for the qubit-only baseline. These results suggest that qutrits offer a promising path toward extending the frontier of quantum computers.

An intense trade-off arises between testing, hardware and speed of electronic circuits. An efficient design for testability methodology for the detection of stuck-at faults in reversible circuits is presented in this paper by exploiting the properties of Toffoli and Fredkin gates. An ( $$n+1$$ ) dimensional general test set depicted in the paper is found complete for the detection of single and multiple stuck-at faults in the modified circuit. A set of benchmark circuits are taken for experimentation where the proposed work achieved a reduction up to $$25.0\%$$ in gate cost and $$35.8\%$$ in quantum cost when compared to the existing work of the area that proves its efficacy towards the reduction in hardware cost with limited degradation in speed.

The theory of logical gates in quantum computation has inspired the development of new forms of quantum logic based on the following semantic idea: the meaning of a formula is identified with a quantum information quantity, represented by a density operator. At the same time, the logical connectives are interpreted as operations defined in terms of quantum gates. In this framework, some possible relations between fuzzy representations based on continuous t-norms for quantum gates and the probabilistic behavior of quantum computational finite-valued connectives are investigated. In particular, a fuzzy-type representation for quantum many-valued extensions of the gates introduced by Toffoli, Fredkin and Peres is described.

It is very important to detect and correct faults for ensuring the validity and reliability of these circuits. In this regard, a comparative study with related existing techniques is undertaken. Two techniques to achieve the testability of reversible circuits are introduced that have been improved in terms of quantum cost and fault coverage rate. Considering this aspect, the main focus of these techniques is on the efficient detection and location of faults with 100% accuracy. These techniques for fault detection in reversible circuit design, in addition to being able to produce the correct outputs, can also provide information for fault location that has already been done at a higher cost. Proposed approaches have been successfully tested for all types of SMGF, MMGF, PMGF, RGF, and SBF. In order to verify the functional correctness of the proposed scheme, it also has executed the testing over a reversible full adder circuit, and findings are checked. In the following, the proposed approach of reversible sequential circuits is presented for the first time so far. The cost metrics are evaluated for all the proposed designs and compared the estimated results against some existing design approaches of reversible circuits for better understanding.

Quantum computers will have a significant impact on the security aspects of many conventional cryptographic algorithms as the quantum circuit implementation of the cryptographic algorithms can be attacked with the help of Grover’s key search algorithm. This work proposes quantum circuit design of RECTANGLE lightweight cipher for 80-bit and 128-bit key variants. All the individual modules of the cipher are designed with minimal quantum resources and finally they are integrated together to build the complete quantum circuit. The quantum circuit synthesis is performed with Toffoli family of quantum gates. The proposed design outperforms the existing design by achieving low-latency. The quantum resources are also estimated to mount the quantum attack by using Grover’s key search algorithm.

We are observing in this pandemic situation of COVID-19 the world in very challenging and to solve this complex problem in quick time. Today, we are facing a difficult complex problem such as Coronavirus. This Coronavirus affects human life. Quantum computing is the only support that can give us quick results by processing the Coronavirus compound at high computation speed. Whatever present circuits in VLSI domain, we cannot perform the high-speed computation and not tackle the complex case as present COVID-19. In this article, we have been discussed about quantum computing era during the pandemic situation of COVID-19. Further, this paper presents fundamental about quantum properties such as superposition, entanglement, and quantum programming tools such as Qiskit (IBM), pyQuil (Google), ProjectQ (ETH), Revkit, and RCvewier +. We have presented quantum circuit and its decomposed circuit of such gates as Toffoli, Fredkin, Peres, and new fault tolerance. In addition, we proposed algorithm as transforming cascade to the quantum circuit which is extended for verification based. All these concepts presented here will be very useful to researcher, academician, and industry person to tackle this pandemic situation of COVID-19. © 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

The works that have been devoted to the topic of quantum computer design have been examined. The main issues surrounding the development of a quantum computer are explored. The “up to bottom” concept has been presented and supported as a fundamentally novel way to solve the problem of building a really quantum computer. The technique can be accomplished by using nanotriggers made of two-dimensional materials, such as graphene, to visualise the quantum states of qubits in advance. This refers to the visualisation (materialisation) of all states, including entangled states, which primarily determine the quantum computer's theoretically large mathematical resource. The proposal is for an electronic device block diagram based on “a priory” quantum states of q-bits. It is demonstrated that each realised (visualised) Shor's cell should correspond to an element of the electronic system for the execution of quantum computation procedures. A block containing at least 1010 nanotriggers that act as q-bits in quantum computation and are generated using graphene nanoribbons and controlled by a specific element is included in the device. The latter is a self-organizing quantum dot with two essentially different magnetic states. This quantum dot is made from a compound whose molecules are distinguished by intramolular rearrangement. Nanotriggers are used to create reversible logic gates or blocks. Three triggers are included in each gate to perform logical operations. The offered device is an additional electronic unit implanted in a digital computer that allows the computational process to be implemented in accordance with the requirements of quantum physics.

We report a proof-of-concept demonstration of a quantum order-finding algorithm for factoring the integer 21. Our demonstration involves the use of a compiled version of the quantum phase estimation routine, and builds upon a previous demonstration by Mart\'in-L\'{o}pez et al. in Nature Photonics 6, 773 (2012). We go beyond this work by using a configuration of approximate Toffoli gates with residual phase shifts, which preserves the functional correctness and allows us to achieve a complete factoring of N=21. We implemented the algorithm on IBM quantum processors using only 5 qubits and successfully verified the presence of entanglement between the control and work register qubits, which is a necessary condition for the algorithm's speedup in general. The techniques we employ may be useful in carrying out Shor's algorithm for larger integers, or other algorithms in systems with a limited number of noisy qubits., Comment: 11 pages, 10 figures, appendix

In distributed quantum computation, quantum remote-controlled gates are used frequently and applied on separate nodes or subsystems of a network. One of the universal and well-known controlled gates is the n-qubit controlled-NOT gate, especially Toffoli gate for the case of three qubits, which are frequently used to synthesize quantum circuits. In this paper, we considered a more general case, an n-qubit controlled-U gate, and present a general protocol for implementing these gates remotely with minimum required resources. Then, the proposed method is applied to implement a Toffoli gate in bipartite and tripartite systems. In this method, we considered cases in which a group of qubits belongs to one subsystem of the network. Then, we improved its consumption resources.

To quantify security levels in a postquantum scenario, it is common to use the quantum resources needed to attack the Advanced Encryption Standard (AES) as a reference value. Specifically, in the National Institute of Standards and Technology's ongoing postquantum standardization effort, different security categories are defined that reflect the quantum resources needed to attack AES-128, AES-192, and AES-256. This article presents a quantum circuit to implement the S-box of AES. Also, leveraging an improved implementation of the key expansion, we identify new quantum circuits for all three AES key lengths. For AES-128, the number of Toffoli gates can be reduced by more than 88% compared to Almazrooie et al. 's and Grassl et al. 's estimates while simultaneously reducing the number of qubits. Our circuits can be used to simplify a Grover-based key search for AES.

Data hiding or steganography has been used ever since a secret message was needed to be transferred. Data hiding methods need a medium to be cover for secret message that is to be sent. Different mediums are used such as image, video, audio, and last decade the deoxyribose nucleic acid (DNA). In this paper, a new data hiding approach based on the DNA sequence is proposed. Unlike many existing methods, the proposed method does not change the biological functionality of the DNA reference sequence when the sequence is translated into amino acids. The proposed method is consisting of two steps: the first step is encrypting the message using the Toffoli quantum gate. The second step is embedding the encrypted message into DNA sequence by taking one codon at a time and considering amino acids' biological functionality during the embedding process. Experimental results show that the proposed method outperforms the existing schemes preserving biological functionality in terms of cracking probability, and hiding capacity for bit per nucleotide.

In this paper, firstly we propose a new protocol for quantum bidirectional teleportation of two particles in a six-qubit entangled channel, which is based on GHZ measurement and unitary operation. Then, also based on the six-qubit entangled state channel, a protocol for quantum bidirectional teleportation of two-three particles is proposed. The protocol utilizes Toffoli gate to convert three-qubit states into two-qubit states and a single qubit, and the rest of the teleportation is the same as the first protocol. Finally, we introduce an auxiliary bit to restore the state of the sender. Both these proposed protocols are more efficient than others in the same situation, which will be compared at the end of the paper.

Since reversible logic has promising applications in domains like low-power design and quantum computing, it is necessary to efficiently design high-performance reversible logic circuits. In this paper, in order to reduce the number of qubits while achieving low quantum cost, the Kronecker functional decision diagram (KFDD) based reversible circuit synthesis method is improved by using two strategies. One is to generate a locally optimal reversible cascade for each of the KFDD nodes by performing transformations on the function represented by a node and using a gate library consisting of NOT, CNOT, Toffoli gates and mixed-polarity Peres gates. This strategy helps reduce the quantum cost and the number of qubits. The other is to map KFDD nodes to their locally optimal reversible cascades level by level via breadth-first traversal of the KFDD. This strategy reduces the number of qubits by using the circuit line labeled by an input variable of the KFDD as the target line of a reversible gate. Comparison results are presented in tabular and graphical forms. Compared to the existing decision diagram based reversible circuit synthesis methods, the proposed method can reduce both the quantum cost and the number of qubits in many cases. Compared to other state-of-the-art synthesis methods for reversible circuits, the proposed method can achieve much lower quantum cost but still incurs a high number of qubits for many functions. However, it can achieve the minimum number of qubits for a few irreversible functions while achieving much lower quantum cost. In addition, the proposed method is very time efficient.

Building a quantum computer is a daunting challenge since it requires good control but also good isolation from the environment to minimize decoherence. It is therefore important to realize quantum gates efficiently, using as few operations as possible, to reduce the amount of required control and operation time and thus improve the quantum state coherence. Here we propose a superconducting circuit for implementing a tunable system consisting of a qutrit coupled to two qubits. This system can efficiently accomplish various quantum information tasks, including generation of entanglement of the two qubits and conditional three-qubit quantum gates, such as the Toffoli and Fredkin gates. Furthermore, the system realizes a conditional geometric gate which may be used for holonomic (non-adiabatic) quantum computing. The efficiency, robustness and universality of the presented circuit makes it a promising candidate to serve as a building block for larger networks capable of performing involved quantum computational tasks., Scientific Reports, 9 (1), ISSN:2045-2322

In recent years, design of low power high-speed nano computing systems have drawn more attention. Reversible Logic is a technique popularly used to design the computing systems to achive them. In a computer, the arithmetic logic unit (ALU) is the fundamental computing module. In this paper, a novel Reversible Arithmetic and Logic Unit is proposed, where a single module performs both arithmetic and logical operations. The possible arithmetic operation includes transfer, addition with carry, subtract, complement and increment. The possible logical operations are AND, OR, XOR, COPY and CONSTANT. The control signal is a key element which defines and alters the data path in order to produce either arithmetic or logical output. The fault-tolerant KMD gates are utilized to construct the ALU. Here, two approaches are discussed for the construction of ALU. In the first approach, ALU is constructed using KMD gates only, whereas in the second approach, combination of KMD, Toffoli and Fredkin gates are used. The functional realization is performed in Quantum Cellular Automata. Quantum circuit is also derived for the same. The obtained results are evident for the improved Quantum cost up to 69%, Constant input up to 40% and Number of gates up to 21% compared to the existing designs.

In this paper, an attempt is made to present a method of quantum cost minimization or optimization technique for quantum reversible circuits using proposed merger rules in Exclusive Sum of Product (ESOP) method. These modified ESOP methods are used to minimize the quantum circuits. We found that the quantum cost is drastically decreased than the previous ESOP method. It will be easy to find the quantum cost and quantum gate optimized quantum circuits implementation. It will also reduce quantum error while the quantum circuit is executed in real quantum processor.

Recently there has been a growing interest in the applicability of reversible circuits. Reversible circuits are designed using reversible gates, which can efficiently reconstruct the previous state of the computation from the current state. These circuits may find potential applications to the future generation of optical and quantum computers. To ensure the reliability of these circuits, testing is a mandatory phase of the design cycle. Several fault models have been introduced for reversible circuits among which some of them have been taken from the conventional circuits. In this paper, we consider the problem of testing bridging faults (such as single and multiple input bridging faults, single and multiple intra-level bridging faults) in a reversible circuit designed with the NOT, CNOT, Toffoli gates (NCT library) and generalized (n-bit) Toffoli gates (GT library). We propose an Automatic Test Pattern Generation (ATPG) method using the Path-Level expression for generating the minimal complete test set to detect the faults mentioned above. The analysis of the experimental results shows that the proposed method has 100% fault coverage, and test set size is smaller than the existing methods.

Ternary reversible logic synthesis has started gaining the attention of researchers in recent years because of its distinct advantages over binary reversible logic synthesis. However, the existing methods for the synthesis of ternary reversible logic circuits are applicable only to smaller benchmarks. The present paper proposes an efficient synthesis approach in this regard using ternary decision diagrams (TDDs). A TDD is first generated for the function that is to be synthesized. Then, using a gate library of ternary reversible gates, each TDD node is mapped to a sequence of ternary reversible gates that are finally merged together to form the required netlist. The ternary gate library consists of ternary reversible gates such as multi-polarity ternary Feynman gate and multi-polarity ternary Toffoli gate. To estimate the quantum cost, we propose a decomposition approach to represent a ternary reversible gate in terms of ternary elementary gates. We have carried out experimental evaluation on two types of benchmarks. The first type consists of binary reversible benchmarks converted into ternary reversible benchmarks using a transformation approach. The second type is based on ternary non-reversible benchmarks. We have reported the results for benchmarks with up to 13 inputs with a longest runtime of 7 min, which compares favourably with the existing works in the literature.

In accordance with Moore’s law, the size of complementary metal oxide semiconductor (CMOS)-based devices keep shrinking to augment the density on the chip. This scaling influences the execution of CMOS device due to several constraints like energy dissipation and synchronization of different components of the device. In non-reversible logic gates, power loss is the major concerned. Interest in reversible logic-based circuit design is increased as it offers reduced heat dissipation. Quantum dot cellular automata (QCA) is the possible implementation platform for reversible circuits. An encoder is an important component of memory, for address decoding and encoding. In this article, reversible logic-based architecture of 4 to 2 and 8 to 3 priority encoder is proposed and implemented on QCA platform. To design the encoder circuit, a new QCA layout of Feynman gate and Toffoli gate has been employed. The proposed layout of Feynman gate and Toffoli gate outshines the existing state-of-the-art designs. Quantum cost and circuit cost estimation of those encoder circuits are also performed. QCADesigner tool has been used to validate the performance of the proposed QCA reversible encoders.

Quantum circuits of many qubits are extremely difficult to realize; thus, the number of qubits is an important metric in a quantum circuit design. Further, scalable and reliable quantum circuits are based on fault tolerant implementations of quantum gates such as Clifford+T gates. An efficient quantum circuit saves quantum hardware resources by reducing the number of T gates without substantially increasing the number of qubits. This work presents a T-count optimized quantum circuit for integer multiplication with only $4 \cdot n + 1$4·n+1 qubits and no garbage outputs. The proposed quantum multiplier design reduces the T-count by using a novel quantum conditional adder circuit. Also, where one operand to the conditional adder is zero, the conditional adder is replaced with a Toffoli gate array to further save T gates. Average T-count savings of $46.12$46.12, $47.55$47.55, $62.71$62.71 and 26.30 percent are achieved compared to the recent works by Kotiyal et al., Babu, Lin et al., and Jayashree et al., respectively.

Quantum technology is an emerging area of engineering and used in bio-informatics, Cryptography, etc. Reversible logic helps Quantum gates in the computation process. Reversible computation is different from conventional computation as it safeguards data while processing it. Reversible logic is used in contemporary research works on combinational circuits. Encoder and Decoder are critical parts of advanced digital electronic devices, which are used in combinational logic, telecommunication and clock generators which are multi-phased. So, this research work focuses on reversible 3:8 decoder and 8:3 encoder and these designs are further extended to linear error correcting codes mainly hamming codes. Further, this work also proves that proposed encoder/decoder can also be used for Error resilient transmission. The proposed circuits consist of rudimentary reversible gates like CCNOT and CNOT so that analysis can be made easy. The methodology of QUEST is implemented in IBM-Q processor where Garbage outputs and constant inputs are equal to zero.

Noisy Intermediate-Scale Quantum (NISQ) devices fail to produce outputs with sufficient fidelity for deep circuits with many gates today. Such devices suffer from read-out, multi-qubit gate and crosstalk noise combined with short decoherence times limiting circuit depth. This work develops a methodology to generate shorter circuits with fewer multi-qubit gates whose unitary transformations approximate the original reference one. It explores the benefit of such generated approximations under NISQ devices. Experimental results with Grover's algorithm, multiple-control Toffoli gates, and the Transverse Field Ising Model show that such approximate circuits produce higher fidelity results than longer, theoretically precise circuits on NISQ devices, especially when the reference circuits have many CNOT gates to begin with. With this ability to fine-tune circuits, it is demonstrated that quantum computations can be performed for more complex problems on today's devices than was feasible before, sometimes even with a gain in overall precision by up to 60%.

We use the IBMQ machine to implement a quantum database circuit. The database is made of a single multi- column table with multiple superposed records using Toffoli, CNOT and single quantum qubit gates. We present an optimized quantum circuit which allows us to select an item from the table, according to a specific oracle. Our circuit is based only on a single auxiliary qubit to perform the Selective Inversion (SI) and the Inversion Around the Average (IAA), which constitute the Grover operator. We analyze the difference between the generated transpired circuits while executing the original circuit on different IBMQ machines, namely the Melbourne and Athens quantum machines. We discuss the physical constraints causing the difference between the simulation on the composer and the executions of the circuits on the real IBMQ devices.

It has always happened in human history that when we thought that things were perfect and nothing better can be done or the thing will suffice us forever some problems unforeseen came up same is the case with CMOS (Complementary Metal Oxide Semiconductors), now researchers are looking beyond CMOS to QCA (Quantum-dot Cellular Automata), a technique which was formulated out of the applications of quantum mechanics. Talking about QCA it is an ingenious technique to fabricate new generation processors and other combinational and sequential circuits. The eye-catching and commercially useful properties of QCA that set it apart from any other technique is its extremely low power consumption in meV, small size going up to nanometer scale, high frequency operation (THz) and elimination of short channel effect. Quantum computing aims to use QCA as the building block for upcoming devices. In this paper, we have improved on the design of the Toffoli gate which is a reversible universal gate. We have successfully improved it on parameters such as cell count by more than 20%, total area by 34%, cell area by 29% and we have maintained latency and complexity as the previous optimal designs even by having less cell count. These improvements will help reduce the size of the chip and reduce power dissipation and thus improve efficiency and be compliant with the ever-increasing computational ability and downscaling requirements.

The synthesis and optimization of quantum circuits are essential for the construction of quantum computers. This paper proposes two methods to reduce the quantum cost of 3-bit reversible circuits. The first method utilizes basic building blocks of gate pairs using different Toffoli decompositions. These gate pairs are used to reconstruct the quantum circuits where further optimization rules will be applied to synthesize the optimized circuit. The second method suggests using a new universal library, which provides better quantum cost when compared with previous work in both cost015 and cost115 metrics; this proposed new universal library “Negative NCT” uses gates that operate on the target qubit only when the control qubit’s state is zero. A combination of the proposed basic building blocks of pairs of gates and the proposed Negative NCT library is used in this work for synthesis and optimization, where the Negative NCT library showed better quantum cost after optimization compared with the NCT library despite having the same circuit size. The reversible circuits over three bits form a permutation group of size 40,320 (23!), which is a subset of the symmetric group, where the NCT library is considered as the generators of the permutation group.

In this paper we discuss Grover Adaptive Search (GAS) for Constrained Polynomial Binary Optimization (CPBO) problems, and in particular, Quadratic Unconstrained Binary Optimization (QUBO) problems, as a special case. GAS can provide a quadratic speed-up for combinatorial optimization problems compared to brute force search. However, this requires the development of efficient oracles to represent problems and flag states that satisfy certain search criteria. In general, this can be achieved using quantum arithmetic, however, this is expensive in terms of Toffoli gates as well as required ancilla qubits, which can be prohibitive in the near-term. Within this work, we develop a way to construct efficient oracles to solve CPBO problems using GAS algorithms. We demonstrate this approach and the potential speed-up for the portfolio optimization problem, i.e. a QUBO, using simulation and experimental results obtained on real quantum hardware. However, our approach applies to higher-degree polynomial objective functions as well as constrained optimization problems., 11 pages, 15 figures

In classical computation, Toom–Cook is one of the multiplication methods for large numbers which offers faster execution time compared to other algorithms such as schoolbook and Karatsuba multiplication. For the use in quantum computation, prior work considered the Toom-2.5 variant rather than the classically faster and more prominent Toom-3, primarily to avoid the nontrivial division operations inherent in the latter circuit. In this paper, we investigate the quantum circuit for Toom-3 multiplication, which is expected to give an asymptotically lower depth than the Toom-2.5 circuit. In particular, we designed the corresponding quantum circuit and adopted the sequence proposed by Bodrato to yield a lower number of operations, especially in terms of nontrivial division, which is reduced to only one exact division by 3 circuit per iteration. Moreover, to further minimize the cost of the remaining division, we utilize the unique property of the particular division circuit, replacing it with a constant multiplication by reciprocal circuit and the corresponding swap operations. Our numerical analysis shows that the resulting circuit indeed gives a lower asymptotic complexity in terms of Toffoli depth and qubit count compared to Toom-2.5 but with a large number of Toffoli gates that mainly come from realizing the division operation.

In this paper, a novel reversible Toffoli gate that uses enhanced logic primitives is proposed. These primitives considered are three-input NAND-NOR-Inverter (NNI) gates and five-input majority-of-five gates. The Toffoli gate design is implemented without any inversion operation, which results in area and delay advantages. Furthermore, we adopt the proposed Toffoli gate as the building block to construct a 4–2 reversible priority encoder. Quantum-dot cellular automata technology was used to validate the proposed design. The experimental results show that the proposed design reduces the delay and the area by 46.15% and 28.71%, respectively, compared with the state-of-the-art design.

As a basic operation in quantum computers, quantum logic gates and particularly controlled NOT (CNOT) gates are important in quantum information processing. In this paper, we propose a one-step scheme to generate a CNOT gate via transitionless quantum driving. In this scheme, an effective Hamiltonian is obtained based on quantum Zeno dynamics to drive the system to evolve into the target state when the parameters are reasonably set. The results of explicit numerical simulations indicate that the proposed scheme is robust against instability related to variation in experimental parameters and decoherence. The scheme can also be extended to generate a Toffoli gate, which is useful for large-scale quantum computers. Moreover, the generation process involves only a single step, greatly simplifying its implementation.

In today’s digital era, developing digital circuits is bounded by the research towards investigating various nano devices. This paper provides the design of compact Baugh-Wooley multiplier using reversible logic. Even though various researches have been done for designing reversible multiplier, this work is the first in the literature to use Baugh-Wooley algorithm using reversible logic. In this work, a new 5 × 5 reversible multiplier cell is proposed which will be useful in designing Baugh-Wooley multiplier. The proposed single multiplier cell is able to perform addition of a 1 × 1 product with the sum and carry from the previous cell. This reversible multiplier cell is useful in building up regularity in the array multipliers. The Toffoli gate synthesis of the proposed reversible multiplier cell is also given. It is comprehended that the number of gates, the constant inputs and garbage outputs values are fewer in number in the proposed design compared to the existing approaches. The design can be enhanced to construct n × n reversible Baugh-Wooley multiplier circuit.

Quantum is an emerging technology in future computers. Reversibility is the main advantage of quantum computers. In conventional computers, the computation is irreversible i.e. the input bits are lost once the logic block generates the output and input bits cannot be restored but it can be done in reversible computation because in reversible computation the inputs and outputs have a one-to-one correspondence. Therefore, a reversible gate input could even be uniquely determined from their output which leads to less power consumption. Hence the complexity of the digital circuits can be reduced by using reversible computing. In quantum computer to perform reversible operations, we need to implement the reversible gates using quantum gates. In this paper, we discussed various reversible logic gates like Feynman, Toffoli, R, Peres and TR gates using basic quantum gates like CNOT, Pauli, Swap gates and their implementation using IBM quantum experience.

We usually use Mixed-Polarity Multiple-Control Toffoli (MPMCT) gates to realize large control logic functions for quantum computation. A logic circuit consisting of MPMCT gates needs to be mapped to a quantum computing device that has some physical limitation; (1) we need to decompose MPMCT gates into one or two-qubit gates, and then (2) we need to insert SWAP gates such that all the gates can be performed on Nearest Neighbor Architectures (NNAs). Up to date, the above two processes have been independently studied intensively. This paper points out that we can decrease the total number of the gates in a circuit if the above two processes are considered dynamically as a single step; we propose a method to inserts SWAP gates while decomposing MPMCT gates unlike most of the existing methods. Our additional idea is to consider the effect on the latter part of a circuit carefully by considering the qubit layout when composing an MPMCT gate. We show some experimental results to confirm the effectiveness of our method.

Black-box quantum state preparation is a fundamental primitive in quantum algorithms. Starting from Grover, a series of techniques have been devised to reduce the complexity. In this work, we propose to perform black-box state preparation using the technique of linear combination of unitaries (LCU). We provide two algorithms based on a different structure of LCU. Our algorithms improve upon the existed best results by reducing the required additional qubits and Toffoli gates to 2log(n) and n, respectively, in the bit precision n. We demonstrate the algorithms using the IBM Quantum Experience cloud services. The further reduced complexity of the present algorithms brings the black-box quantum state preparation closer to reality., Comment: 13 pages, 3 figures

Multiplier is one among the essential hardware blocks in present-day communication and digital signal processing (DSP) systems. The primary advantage of Vedic multiplier is that delay increases slowly with the increase of input bits. Vedic multiplier has supreme advantage when compared with other multipliers over regularity of structures and gate delays. In this paper, the different designs of 8 * 8 bit Vedic multiplier are implemented with different adders, and these multipliers and adders are structured using suitable reversible logic gates, that is, Feynman gate, Peres gate, Toffoli gate, DPG gate and modified Fredkin gate. The different designs of Vedic multipliers designed with the help of different adders, that is, ripple carry adder, carry skip adder and carry select adder, and hence compared their implementation time as well as area required for the circuitry. This comparison will help designers to choose the preferable multiplier according to the application specific demands.

Each and every day new technology is being established which is miniaturized and challenging the low power than existing design. All the gates used in the design is reversible to achieve low power and less complexity. In past few decades reversible enlarges its applications in modern computing environment. Reversible gates can be executed using any Boolean function. In a modern computing environment adders plays important role for addition process as well as for subtraction. This paper proposes a modified reversible parallel and serial adder/subtraction circuit using Dual Key Gate (DKG) and SG gate. The performance of parallel adder/subtractor circuit design using dual key gate and serial adder/subtractor using dual key gate with SG gate is simulated and synthesized using Xilinx. The performance of this circuit is compared with existing design using Feynman gate and toffoli gate based on complexity, low power and Garbage input/outputs.

The paper introduces new Toffoli and Peres reversible gates, which operate under disjunctive control, and shows their functionality based on the Barenco et al. quantum model. Both uniform and mixed polarity are considered for the controls. Rewriting rules are presented, which provide a reduction of the number of gates and quantum cost of reversible (sub) circuits using standard Toffoli or Peres gates. It is shown that in most cases a reduction in the number of CNOT gates is obtained, which is convenient when mapping reversible circuits to IBM-QX quantum computers.

Toffoli and Peres reversible gates are known to operate based on the conjunction of the control signals. It will be recalled that a disjunctive control is also possible although not well known. The main focus of the chapter will be on the realization of these gates, which at least at the symbolic level will have a mixture of conjunctive and disjunctive control. This will be called hybrid control. Straightforward realizations as well as efficient realizations based on a Barenco et al. type quantum model will be presented. Some aspects of scalability will be discussed.

Quantum computing is a newly emerging computing environment that has recently attracted intense research interest in improving the output fidelity, fully utilizing its high computing power from both hardware and software perspectives. In particular, several attempts have been made to reduce the errors in quantum computing algorithms through the efficient synthesis of quantum circuits. In this study, we present an application of an optimization model for synthesizing quantum circuits with minimum implementation costs to lower the error rates by forming a simpler circuit. Our model has a unique structure that combines the arc-subset selection problem with a conventional multi-commodity network flow model. The model targets the circuit synthesis with multiple control Toffoli gates to implement Boolean reversible functions that are often used as a key component in many quantum algorithms. Compared to previous studies, the proposed model has a unifying yet straightforward structure for exploiting the operational characteristics of quantum gates. Our computational experiment shows the potential of the proposed model, obtaining quantum circuits with significantly lower quantum costs compared to prior studies. The proposed model is also applicable to various other fields where reversible logic is utilized, such as low-power computing, fault-tolerant designs, and DNA computing. In addition, our model can be applied to network-based problems, such as logistics distribution and time-stage network problems.

Current quantum computers are especially error prone and require high levels of optimization to reduce operation counts and maximize the probability the compiled program will succeed. These computers only support operations decomposed into one- and two-qubit gates and only two-qubit gates between physically connected pairs of qubits. Typical compilers first decompose operations, then route data to connected qubits. We propose a new compiler structure, Orchestrated Trios, that first decomposes to the three-qubit Toffoli, routes the inputs of the higher-level Toffoli operations to groups of nearby qubits, then finishes decomposition to hardware-supported gates. This significantly reduces communication overhead by giving the routing pass access to the higher-level structure of the circuit instead of discarding it. A second benefit is the ability to now select an architecture-tuned Toffoli decomposition such as the 8-CNOT Toffoli for the specific hardware qubits now known after the routing pass. We perform real experiments on IBM Johannesburg showing an average 35% decrease in two-qubit gate count and 23% increase in success rate of a single Toffoli over Qiskit. We additionally compile many near-term benchmark algorithms showing an average 344% increase in (or 4.44x) simulated success rate on the Johannesburg architecture and compare with other architecture types., Comment: In ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 12 pages, 12 figures