Search

An Objective-Flexible Clustering Algorithm (OFCA), which is applicable to multiple design objectives and targets high performance and low energy task mapping and scheduling on homogenous cluster-based NoC, is presented. OFCA employs a lineal clustering to group tasks into clusters, and utilizes an efficient heuristic task mapping process to allocate ready clusters onto the platform. Then a low latency pipeline-based static task scheduling stage is proposed to arrange task sequence in IP cores. Finally a best hardware resource demand for the application could be predicted for reference. OFCA can fully exploit the parallel characteristics within task graphs to minimize inter-cluster communication and limit copying tasks when clustering to reduce extra execution energy. It also controls the use of task-duplication-technique (TDT) by setting different parameters for flexible goals to make a compromise between energy and latency. Experiments show that objectives can be adjusted via different parameter ratios performing OFCA and 57% energy savings on average can be achieved compared to CM Algorithm when employed to streaming applications of 18, 36, and 40 tasks.

More and more computing cores will be integrated in the future SoC to deal with the growing application requirement. For such Multi-Processor System-on-Chip (MPSoC) with high integration and large complexity, one key issue is the on-chip communication among various cores. By the way of analyzing the communication process, this paper proves that the bottleneck of inter-core communication is the interaction between computing and communicating element. Targeting high efficiency of such interaction, a novel interaction strategy which combines a Lookup Table (LUT) mechanism and DMA mode, is proposed. In this strategy, a hardware message address table is created in the network interface (NI), and NI can transfer the data from the network to local memory directly by looking up this table. It can remarkably reduce the usage of CPU interruption during communication, which is significant to improve the communication performance. The experimental results show that the proposed strategy brings better performance than the traditional buffer pool strategy when the message size is big, and performs the same when the message size is small.

A new scalable Metal-Insulator-Metal (MIM) capacitor model is presented for RF (Radio Frequency) applications. Four MIM capacitors were fabricated in 0.13 U m CMOS technology. Using physical analysis based on the new model, parameter optimization and curve fitting, the scaling rules are given for all elements on the circuit model. The model fits very well with the measured data in the frequency range 500 MHz-10.01 GHz. The results show that the proposed model provides accurate results, while retaining the physical properties of every element in the model.

A low-cost BIST scheme based on linear histogram for testing ADC is presented in this paper. A parallel time decomposition technique is presented to minimize not only hardware overhead but also testing time of the BIST scheme based on histogram. An area-efficient linear triangular waveform generator is discussed as test stimulus. The technique uses digital delta-sigma noise shaping to generate the on-chip precise analog stimulus and simplify the analog circuit of the generator at same time. A practical implementation is described and the performance is evaluated

With the scaling of CMOS, the system-on-chip (SOC) has become a viable option for RF system. The absence of high Q inductors for CMOS RF has led to an appearance of RF system-in-package. In this paper, we analyze the merit of the package for CMOS RF IC and review development of the package. We focus on LTCC technology and simulate a high performance mixer using stacked spiral inductor.

With the development of trusted computing systems, TCG promotes TPM as the core hardware building block. The SHA-1 engine in TPM contributes the performance of the whole platform. In this paper, the data flow latencies of the SHA-1 hardware implementation are analyzed, and the bottlenecks are optimized by special arithmetic structures. As a result, the frequency of the optimized structure has increased by 43%. And the performance of this SHA-1 engine is also compared with other SHA-1 engines by frequency, area and throughput.

A concatenated decoder mainly composed of depunctured Viterbi decoder, convolutional deinterleaver, and Reed-Solomon decoder is presented. It has very wide applications in DVB, HDTV and satellite communication systems. In the convolutional interleaver, an over-clocking scheme is employed to guarantee the speed limits. The algorithms of Viterbi decoder and RS decoder are modified T-algorithm and modified Euclidean algorithm, respectively. Furthermore, the finite field multipliers and inversion over composite fields was adapted to optimize area and power in RS decoder, which reduced the area near to 25% compared to the conventional finite fields. The proposed concatenated decoder has about 81,000 gates except RAM model, which are implemented in 100 MHz using 0.25 um CMOS process.

This paper presents a new architecture of punctured Viterbi decoder with high-speed and low-power based on the modified T-algorithm and trace-back method. To gain high throughput and short decoding latency, parallel computations in ACSU and SMU are adopted. Furthermore, to save the power consumption, the unnecessary computations of path metric are omitted in the add-compare-select-unit (ACSU) and the already generated back-tracing routes are reused to reduce the times of trace-back operations in the survivor-memory-unit (SMU). The decoding latency of the (2,1,7) Viterbi decoder is only 34 clock cycles, the total average power is 185 mW with 200 Mb/s throughput using 0.25 /spl mu/m CMOS technology.

This paper presents a new VLSI design and implementation of a high-speed three-stage pipelining Reed-Solomon (204,188) decoder based on the modified Euclidean algorithm (MEA). A new multiplier and inversion for GF(2/sup m/) are implemented on the composite field GF(2/sup 2n/) (m = 2n), which offers no more than 75% hardware requirements of the standard Mastrovito multiplier and ROM respectively. By setting the new initial conditions of MEA, a novel parallel MEA architecture is proposed to reuse the registers and multipliers, which can save about 30% hardware overheads compared to the conventional architecture with the same decoding rate. Using 0.25 /spl mu/m CMOS technology, the complexity of the proposed RS decoder is about 30,000 gates with the decoding latency of 239 clock cycles and a throughput of 1.6 Gbit/s.

This paper presents a new VLSI design and implementation of a high-speed three-stage pipelining Reed-Solomon decoder based on the modified Euclidean algorithm. A new multiplier and inversion for GF(2/sup m/) are implemented on the composite field GF(2/sup 2n/) (m=2n), which offers lower hardware requirements compared to standard Mastrovito multiplier and ROM respectively. By setting the new initial conditions of MEA, not only decoding latency but also hardware overheads of RS (204,188) decoder is reduced greatly compared to the conventional architecture with the same decoding rate. The complexity of the proposed RS decoder is about 118,000 gates, and the decoding latency is only 220 clock cycles and has a throughput of 800 Mbit/s using 0.25 /spl mu/m CMOS process.

The SoC (system-on-chip) based on reusable embedded IP (Intellectual Property) introduces new challenges for the test, since the SoC integrator may not know the implementation of the IP cores that are usually embedded in chip deeply. IEEE P1500 standard for embedded core test (SECT) is a standard-under-development that aims at improving ease of testing SoC. The SECT standardizes the core wrapper and the core test language (CTL), and leaves the design of test access mechanism (TAM) to the SoC integrator. The TAM-bus we proposed is a P1500 compliant TAM. This paper describes the control of TAM-bus. With a novel interface to the chip level JTAG test access port (TAP), the TAM control module can provide the control of the TAM and wrappers. The final test architecture is flexible and configurable. The test architecture we presented has been implemented in an industry SoC. The test coverage remains 99.40%. The hardware overhead increases only 0.17% due to the TAM-bus and the TAM controller. The experiment results demonstrate that the test architecture can offer the solution for testing SoC.

This paper presents an efficient motion compensation architecture for MPEG-4 advanced simple profile at level 5 (ASP@L5) streaming video standard. A novel local memory storage scheme for motion vector prediction is proposed in the paper. In this scheme, local memory for storing differential data of motion information in video packet layer is avoided, and total memory access bandwidth is reduced 1/3. The motion compensation unit is implemented using 0.25mm 1-poly 5-metal CMOS technology, which occupies a silicon area of 1.35t1.35 mm2 and operates at 150MHz. Simulation result shows that it is capable of compensating AS profile sequences at ITU-601 resolution video in real time.

Utilizing a core-centric approach, we can develop plug-compatible components and greatly maximize design reuse. IP blocks and buses with standard core interface can be plugged directly together with little or no custom interfacing, saving an amount of design time. This article presents the design of AMBA AHB/VCI wrapper which is intended for connecting VCI-based cores to the AMBA AHB bus. The paper details the comparison and contrast between the AMBA AHB bus protocol and BVCI interface protocol. The two key techniques: quasi-pipelined operation and pre-fetching is proposed to reduce performance overhead. We also take its configurability into consideration to enhance the flexibility of application. Finally, the paper discusses the practicability of VCI usage with an on-chip bus.

A pipeline VLSI design of FFT based on Good-Thomas algorithm is presented, to implement FFT with 255 points in GF(256), this design only needs 60 eight bits galois multipliers, a ROM to store 30 twiddles and some registers. The latency is 255+17 clock cycles, and the maximum combination delay is the sum of one multiplier in GF(256) and four stage XOR gates. This design is modular, regular, simple and suitable for VLSI implementation.

In this paper we presented a method to improve the performance of augmented L1 data cache, mainly based on the NTS scheme. The new structure (called MNTS cache) contained three main features different from NTS cache: adding locality status to augment the practical boundary, attaching a detect unit to the small buffer for more precise locality detection, and changing the NT-buffer to dual functionality uses. The theoretical model verified the effectiveness of MNTS scheme, and the simulations results proved its performance was generally better than NTS cache.

Presented a concatenated encoder that has very wide applications in DVB, HDTV and satellite communication systems. It was mainly composed of punctured convolutional encoder, convolutional interleaver, and Reed-Solomon encoder. In the convolutional interleaver, an over-clocking scheme is employed to guarantee the speed limits. Furthermore, a finite field multiplier of composite fields was adapted to optimize area and power in RS encoder, which reduced the area near to one half compared to the conventional RS (204,188) encoder. The proposed concatenated encoder has about 3700 gates except RAM model and it has good compliance with EN300 421.