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This work reports 2-bits/cell hafnium oxide-based stacked resistive random access memory devices fabricated on flexible polyimide substrates for neuromorphic applications considering the high thermal budget. The ratio of low-resistance state current (${I}_{ \mathrm{\scriptscriptstyle ON}}$) to high-resistance state current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) or ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ for the fabricated devices was above $1.4\times10$ 3 with a low device-to-device variation at $100 \boldsymbol {\mu }\text{A}$ current compliance. The mechanical stability over 104 bending cycles at a 5 mm bending radius and endurance over 106 WRITE cycles makes these devices suitable for online neural network training. The data retention capability over 104s at 125°C also infuses these devices’ long-term inference capability. Furthermore, the performance of the devices has been verified for neuromorphic applications by system-level simulations with experimentally calibrated data. The system-level simulation reveals only a 2% loss in inference accuracy over ten years from the baseline. [ABSTRACT FROM AUTHOR]

Nonvolatile memories especially the ferroelectric (FE)-based ones such as ferroelectric tunnel junctions (FTJs) and ferroelectric field-effect transistors (FeFETs) have recently attracted a lot of attention. FTJs have been intensively researched for the last decade and found to be very promising memory devices due to their significant nondestructive readout advantage as compared to conventional ferroelectric random access memory (FRAM). However, more research is needed on FTJ devices to obtain reliable endurance and retention behavior. In this article, we demonstrate the characteristics and performance of zirconium-doped hafnium oxide-based FTJ devices in terms of FE switching and reliability. This is investigated for FTJ stack structure tuning as well as for the FE switching process in FTJ devices. The FTJ memory switching characteristics, the effects of polarization switching on the write conditions, and the impact of pulse width and pulse amplitude on switching are investigated. The impact of FE layer thickness and interface layer type/thickness are reported to obtain a maximum FTJ ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio (memory window) and reliable performance. The maximum ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio changes depending on the FE layer (zirconium-doped HfO2 layer) thickness (12, 8, 6, and 4 nm), the interface layer type (SiO2, Al2O3), and thickness (1 and 2 nm), indicating the maximum value of ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio for a 1 nm SiO2 interface layer stack. Moreover, a stable endurance of 104 cycles is reported and extrapolated measurements suggest stable retention for more than ten years. Time-dependent breakdown analysis was performed to investigate the reliability of devices indicating a lifetime of ten years. [ABSTRACT FROM AUTHOR]

One of the critical issues in spintronics‐based technologies is to increase the data storage density. Current strategy is based on shrinking the devices size down to tens of nanometers, or several nanometers, which is reaching its limit. A new proposal is to use multi‐level cells (MLCs) to store more than two bits in each cell. In this work, the multi‐level switching is realized in CoFeB/MgO/CoFeB based nano‐scale single perpendicular magnetic tunnel junctions (p‐MTJs) with three or four stable resistance states. A large range of writing currents for each state is obtained, accompanying with a good repeatability of set‐reset operations between different states. The developed multi‐domain model perfectly matches the experimental results, reflecting the magnetic behaviors during multi‐level switching. Furthermore, current‐driven domain wall (DW) motion is revealed in the circular p‐MTJs, where the DW position can be reversibly manipulated by applied current. To design high‐performance multi‐level p‐MTJs, the parameter diagrams are calculated, suggesting various feasible strategies to improve the multi‐level switching through materials optimization and devices geometry. In summary, the demonstration of multi‐level switching in single p‐MTJ shows the high potential of realizing the new generation of p‐MTJ‐based multi‐level spintronic devices, such as multi‐level memories and spin‐neuron devices. [ABSTRACT FROM AUTHOR]