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This paper presents a new algorithm for image super resolution using image registration and neural network. Our method breaks out the limit of registration-based methods which uses the bicubic interpolation to estimate the missing pixel values. Since bicubic method cannot interpolate these pixels exactly, we need more low-resolution frames at input to increase the super-resolution performance. Our algorithm uses a multi-layer perceptron to get better interpolation. This solution leads to higher quality at high-resolution output image without increasing the input number. Experimental results show that our method improves the performance of image super resolution.

This paper presents FPGA implementation of realtime object segmentation which is applied for Chroma-key effect. In order to implement hardware architecture for real-time segmentation, we propose a method which has two stages consisting of seed selection and modified GrowCut. In the first stage, K-Means clustering method and edge detection are applied to specify automatically seed pixels of the object and the background. In the second stage, GrowCut algorithm which has been modified for real-time processing is applied to label the rest of pixels based the seed pixels. The hardware architecture of the proposed method is designed and implemented on Bitec Cyclone III development kit. The experimental result shows that our system can perform real-time object segmentation on HD videos.

This paper presents a design and implementation of the real-time traffic sign detection and recognition system based FriendlyARM Tiny4412 board. We develop an algorithm for detecting and recognizing the traffic signs in Vietnam with real-time processing capability and high accuracy. To achieve these objectives, we employ three main techniques consisting of traffic sign extraction based on chromatic color segmentation, shape matching, and support vector machine (SVM). Moreover, we apply multi-threading method for quad-core ARM Cortex-A9 processor on FriendlyARM board to enhance the real-time capability of the system. The experimental result shows that our system can detect and recognize the traffic signs with accuracy of 90.1% at 15 frames per second on FriendlyARM Tiny4412 board. The proposed system can be equipped on cars to support drivers tracking traffic signs.

Hand gesture is becoming one of the most common ways that people use in information technology products needing interaction between people and computer, which brings to user an interesting experience. 3D camera are developed recently, e.g. Kinect, not only provide color image, but also depth map. It opens a new opportunity in development of human computer interaction (HCI) application. This paper shows a novel hand gesture recognition method based on depth image obtained from the Kinect sensor. Firstly, the hand region extraction is done by putting thresholds on hand point detected by using NITE 2 library provided by PrimeSense. Secondly, we extract the feature vector including the number of open fingers, the angles between the fingertips and horizontal of the hand, the angles between two consecutive fingers, and the difference between the distance from the hand center to the fingertips and the radius of the biggest inscribed circle. Finally, a support vector machine (SVM) is applied to identify different gestures. The experimental result shows that the proposed method performs hand gesture recognition at accuracy of 95% in real-time.

 Abstract—Chroma-key is an application which is used many in video industries, TV programs. In this paper, we present an efficient algorithm for Chroma-key and its FPGA implementation. In the proposed method, we firstly employ K-means to segment input frames in to a trimap including background, foreground, and unknown regions. In the next stage, we utilize comparison of confident neighborhood pixels to refine unknown region to separate background and foreground regions. In order to apply the proposed algorithm for real-time chroma-key effect, we implement its VLSI architecture on Bitec Cyclone III development board. Our design is able to perform Chroma-key process with pleasing quality HD video in real-time.

This paper presents a new image denoising method using block classification in Contourlet domain. The noise image is divided into 8×8 blocks. These blocks can be decomposed by the Contourlet into directional subbands while the block classification method provides the directional feature of input blocks. Based on this directional information, we propose the different thresholding processes with each input block. Thus, the new denoising algorithm proposed achieves better tradeoff between details retain and noises removal. Several experimental results show that the proposed new function is very effective and gives better performance both in terms of PSNR and in visual quality.

Embedded systems are being further developed and applied in medical devices. In this paper, we present an embedded design for dental intraoral system which supports dental image capturing and image tooth segmentation. This device assists dentists in diagnosis by using dental images, which is captured from dental camera. Moreover, we propose advanced features for the dental intraoral system including touch screen with Vietnamese graphic user interface (GUI), dental image processing, patient records, and dentist's diagnosis note. Especially, the segmentation of teeth is important for examining and extracting teeth features from dental images. A teeth segmentation method based on active contour without edge algorithm has been proposed in this paper. Consequently, our system is portable, economic and ready to be applied at dental clinics. The system can help dentists examine at patient's home and voyages, not only in clinics.

This paper presents a design and implementation of a real-time video denoising on FPGA. The video noise is decomposed into directional subbands by using contourlet transform. Thus, Gaussian noise in video frames can be removed significantly by an adaptive thresholding technique. Besides, to process video in real-time, a hardware design of proposed video denoising is implemented on FPGA. In order to achieve highest throughput, we design full pipeline architecture for hardware design. Experimental results show that our design can process with throughput of up to 150 Megapixels per second, which is totally suitable for high definition (HD) video processing.

Bidirectional motion estimation is an efficient algorithm which can solve the problem of holed and overlapped regions for motion compensated frame interpolation in frame rate up-conversion applications. This paper proposed an efficient VLSI architecture for this algorithm using multi-resolution frames to reduce the hardware resource. The initial motion vectors (MVs) in bidirectional motion estimation are obtained by full-search motion estimation algorithm at the lowest resolution frames. Then, the MVs are refined in small local search in the upper-resolution frames. The buffer is implemented to store the search data of two down-sampled levels. The proposed architecture is synthesized with about 25K gates and 1440 bytes internal memory for the search range of [-16, 16].

In this paper, we propose a new motion compensated frame interpolation algorithm for frame rate-up conversion in multimedia applications. In our proposed method, motion vectors (MVs) are estimated by jointing forward and backward motion estimation, then smoothed and re-estimated by using a spatio-temporal MV smoothing and MV post-refinement. The refinement method is based on the coherence of MV field in both spatial and temporal domain to correct false MVs. Finally, we propose an adaptive motion compensated interpolation to reduce block artifacts in intermediate frame, especially in boundary regions. The experiments show that our algorithm outperforms the conventional methods in term of PSNR and visual quality.

In this paper, VLSI architectures and FPGA implementation for edge-preserving filter are presented. We proposed two architectures for edge preserving filter: full parallel pipelined and structure-shared architectures. The edge-preserving filter uses adaptive coefficient mask based on the intensity distance in filter blocks. Compared with the bilateral filter, the proposed edge-preserving filter provides significantly noise reduction. We implement the proposed architecture on Cyclone II EP2C70F896C8 FPGA device from Altera Corp. Our experiments show that the PSNR improvement is up to 5.3 dB for Gaussian noisy images.

Block artifact is one of the visually annoying problems that usually exist in low-bit-rate compression images or videos. In this paper, we propose a simple but effective method to reduce block artifact based on pixel classification in spatial domain. We classify each pixel into two classes: smooth region and edge region, by using a binary edge map from the edge detection process. An adaptive offset smoothing with the binary edge map is applied to reduce grid noise at block boundaries. Moreover, an extra edge-preserved filter is used to remove block artifacts at edge region. Our experiments show that the proposed method can reduce block artifact effectively more than block-based classification methods.