1. Design and Simulation of VHDL based ARP Cache
- Author
-
Zhu Hong-Feng, Zhou Chuan-Sheng, Liu Tian-Hua, and Chang Guiran
- Subjects
business.industry ,computer.internet_protocol ,Computer science ,Hardware description language ,Functional requirement ,computer.software_genre ,Whole systems ,Internet protocol suite ,Embedded system ,VHDL ,Operating system ,Address Resolution Protocol ,Cache ,business ,computer ,computer.programming_language ,ModelSim - Abstract
In order to working together with ARP module in TCP/IP stack and making sure the high speed of ARP module, in this paper, with hardware language VHDL we re-code the cache portion of ARP protocol. According to the functional requirements of ARP cache by system, we re-code it in Xilinx ISE7.ll intergration environment, and in the meantime we did the simulation test in ModelSim. The simulation test results indicate that the re-designed ARP cache drops down a lot of cost both in space and time. The success of re-design of ARP cache with VHDL, will improve a lot of ARP working efficiency and as results to improve the whole system working speed of TCP/IP stack.
- Published
- 2007