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This paper explores the possibility of using multi-core programming model that implements the Cascade correlation neural networks technique (CCNNs), to enhance the classification phase of 3D facial recognition system, after extracting robust and distinguishable features. This research provides a comprehensive summary of the 3D facial recognition systems, as well as the state-of-the- art for the Parallel Cascade Correlation Neural Networks methods (PCCNNs). Moreover, it highlights the lack of literature that combined between distributed and shared memory model which leads to novel possibility of taking advantage of the strengths of both approaches in order to construct an efficient parallel computing system for 3D facial recognition.

Shared Memory stands out as a sine qua non for parallel programming of many commercial and emerging multicore processors. It optimizes patterns of communication that benefit common programming styles. As parallel programming is now mainstream, those common programming styles are challenged with emerging applications that communicate often and involve large amount of data. Such applications include graph analytics and machine learning, and this paper focuses on these domains. We retain the shared memory model and introduce a set of lightweight in-hardware explicit messaging instructions in the instruction set architecture (ISA). A set of auxiliary communication models are proposed that utilize explicit messages to accelerate synchronization primitives, and efficiently move computation towards data. The results on a 256-core simulated multicore demonstrate that the proposed communication models improve performance and dynamic energy by an average of 4x and 42% respectively over traditional shared memory.

This paper introduces a generic framework for defining instructions, programs, and the semantics of their instantiation by operations in a multiprocessor environment. The framework captures information flow between operations in a multiprocessor program by means of a reads-from mapping from read operations to write operations. Two fundamental relations are defined on the operations: a program order between operations which instantiate the program of some processor and view orders which are specific to each shared memory model. An operation cannot read from the "hidden" pastor from the future; the future and the past causality can be examined either relative to the program order or relative to the view orders. A shared memory model specifies, for a given program, the permissible transformation of resource states. The memory model should reflect the programmer's view by citing the guaranteed behavior of the multiprocessor in the interface visible to the programmer. The model should retrain from dictating the design practices that should be followed by the implementation. Our framework allows an architect to reveal the programming view induced by a shared-memory architecture; it serves programmers exploring the limits of the programming interface and guides architecture-level verification. The framework is applicable for complex, commercial architectures as it can capture subtle programming-interface details, exposing the underlying aggressive microarchitecture mechanisms. As an illustration, we define the shared memory model supported by the PowerPC architecture, within our framework.

Parallel single-level store (PSLS) systems integrate a shared virtual memory and a parallel file system. They provide programmers with a global address space including both memory and file data. PSLS systems implemented in a cluster thus represent a natural support for long-running parallel applications, combining both the natural shared memory programming model and a large and efficient file system. However, the need to tolerate failures in such a system increases with the size of applications. In this paper we present a highly-available parallel single level store system (HA-PSLS), which smoothly integrates a backward error recovery high-availability mechanism into a PSLS system. Our system is able to tolerate multiple transient failures, a single permanent failure, and power cut failures affecting the whole cluster, without requiring any specialized hardware. For this purpose, HA-PSLS relies on a high degree of integration (and reusability) of high-availability and standard features. A prototype integrating our high-availability support has been implemented and we show some performance results in the paper. Copyright © 2003 John Wiley & Sons, Ltd.

Shared Virtual Memory (SVM) systems are organizations of Distributed Shared Memory systems (DSM). These systems offer a shared memory programming model that is more intuitive than the message passing paradigm. Other advantages include low hardware and maintenance costs. This paper introduces a new simulation environment for such architectures. The developed tool is an execution-driven simulator aimed at studying the behavior of memory consistency models, with the exception of those needing compiler modifications. Thus, we propose a cheap and flexible way to design efficient consistency approaches for SVM systems.

The GFLOPS project's aim is to develop a parallel architecture as well as its software environment to implement scientific applications efficiently. This goal can be achieved only with a real collaboration among the architecture, the compiler and the programming language. This paper investigates the C// Parallel language and the underlying programming model on a global address space architecture. The main advantage of our paradigm is that it allows a unique framework to express and optimize both data and control parallelism at user-level. The evaluation of C// has been conducted on a cluster of PCs.

The aim of this presentation is to give an introduction to the field of distributed algorithms in the shared memory model. An execution is considered as a set of elementary actions equiped with two relations satisfying some classical axioms. The notion of register is introduced and constructions of registers from elementary components is given. This survey contains most of the results of L. Lamport's papers On interprocess communication I & II.

In the era of multicore and manycore programming, memory represents a restrictive resource and it is therefore necessary to share as much as possible between processes. But in many cases, in which a parallel execution of an application has never been foreseen, it is difficult to apply a shared memory model afterwards. The KSM-tool (Kernel Same Page Merging) provides an easy ad-hoc-solution to reduce the overall memory footprint. This paper shows that in the applications of the LHCb experiment at CERN between 8% and 48 % of memory can be gained. In addition it will be discussed how to adjust KSM in order to balance the gain in memory and the additional CPU consumption.

Uintah is a software framework that provides an environment for solving large-scale science and engineering problems involving the solution of partial differential equations. Uintah uses a combination of fluid-flow solvers and particle-based methods for solids, together with adaptive meshing and synchronous task-based approach with automated load balancing. When applying Uintah to fluid-structure interaction problems, the combination of adaptive meshing and the movement of structures through space present a formidable challenge in terms of achieving scalability on large-scale parallel computers. Adopting a model that uses MPI to communicate between nodes and a shared memory model on-node is one approach to achieve scalability on large-scale systems.This scalability challenge is addressed here for Uintah, by the development of new hybrid runtime and scheduling algorithms combined with novel lock-free data structures, making it possible for Uintah to achieve excellent scalability for a challenging fluid-structure problem with mesh refinement on as many as 256K cores.

International audience; Checkpointing Aided Parallel Execution (CAPE) is the paradigm we developed to use checkpointing techniques to automatically run parallel programs on distributed-memory architectures. Two versions of CAPE have been developed and tested. The first one was based on complete checkpoints and has proved the feasibility of the paradigm but did not have good performance [1]. The second one based on incremental checkpoints improved performance a lot and made it comparable with MPI similar programs [2]. However, both versions are applicable only to problems containing parallel regions that verify the Bernstein's conditions. In this case data in parallel regions are processed independently in each parallel thread and result are combined at the end of each region. To overcome this restriction, two main tracks have been investigated: the first one consists in implementing a shared-memory model and the second one in processing all requirements of OpenMP data-sharing clauses and directives. In this paper, we present the design of a shared-memory model based on the Home-based Lazy Release Consistency model and the algorithm to implement it

The need for programs to execute subcomponents in isolation from each other or with lower privileges is prevalent among today's systems. We introduce ribbons: a shared memory programming model that allows for more implicit sharing of memory than processes but is more restrictive than threads. Ribbons structure the heap into protection domains. Privileges between these protection domains are carefully controlled in order to confine computation. We propose RibbonJ, a backwards-compatible extension of Java, to easily create or port programs to use the ribbons model. We study the progress and isolation properties of a subset of the language. Building on JikesRVM we implement ribbons by leveraging existing memory protection mechanisms in modern hardware and operating systems, avoiding the overhead of inline security checks and read or write barriers. We evaluate efficiency via microbenchmarks and the DaCapo suite, observing minor overhead. Additionally, we refactor Apache Tomcat to use ribbons for application isolation, discuss the refactoring's design and complexity, and evaluate performance using the SPECweb2009 benchmark.

In recent years hardware accelerators have become a full part of the HPC domain as their peak performance has increased steadily. Although their programmability has greatly improved and different tools have been developed to smooth down their learning curve, porting legacy code to the new programming models could reveal itself a cumbersome and time-consuming process. However a large amount of code benefits from the multicore architectures using either a shared memory model or a distributed model. Our goal was to allow developers to benefit from the simplicity of OpenMP code and at the same time permitting their code to be executed on GPUs many core architectures. Thus we propose a source-to-source compiler able to automatically transform an OpenMP C code into a CUDA code, while maintaining a human readable version of the code that can be further analyzed or optimized. Using the OMPi compiler as a base ground, we implemented the "pragma omp parallel for" transformation along with data visibility clauses. The generated code is fully NVIDIA CUDA compliant and can be compiled using the nvcc compiler. In this paper we present the entire transformation process, starting from the pragma split-up and kernel generation, passing through the data visibility clauses management and ending with the device memory management and kernel launch system.

Multicore systems provide potential to improve the performance of the applications. However, substantial programming effort is required to exploit the power of the parallelism. This paper presents a single source compiler to map the data-parallel programs onto Cell Broadband Engine. Based on the distributed memory model, the compiler performs automatic data distribution and generates SPMD programs with message-passing primitives for Cell. We evaluate our compiler using a range of computation intensive benchmarks, high performance is achieved on Cell platform. In contrast to OpenMP, our method can fully exploit data locality through managing the shared data using inter-processor communication instead of accessing main memory, which significantly reduces the off-chip memory access overhead.

The “holy grail” of parallel software systems is a parallel programming language that will be as easy to use as a sequential one, while maintaining most of the potential efficiency of the underlying parallel hardware. TOP-C (Task-Oriented Parallel C) attempts such a model by presenting a task abstraction that hides much of the details of the underlying hardware. DSM (Distributed Shared Memory) also attemps such a model, but along an orthogonal direction. By presenting a shared memory model of memory, it hides much of the details of message-passing required by the underlying hardware. This article reviews the TOP-C model and then presents ongoing research on combining the advantages of both models in a single system.

It is argued that the choice between the shared-memory and message-passing models depends on two factors: the relative cost of communication and computation as implemented by the hardware, and the degree of load imbalance inherent in the application. Two representative applications are used to illustrate the performance advantages of each programming model on several different shared-memory machines, including the BBN Butterfly, Sequent Symmetry, Encore Multimax and Silicon Graphics Iris multiprocessors. It is shown that applications implemented in the shared-memory model perform better on the previous generation of multiprocessors, while applications implemented in the message-passing model perform better on modern multiprocessors. It is argued that both models have performance advantages, and that the factors that influence the choice of model may not be known at compile-time. As a compromise solution, the authors propose an alternative programming model, which has the load balancing properties of the shared-memory model and the locality properties of the message-passing model, and show that this new model performs better than the other two alternatives. >

Hetero Helix is a programming environment which simulates shared memory on a heterogeneous network of distributed-memory computers. The machines in the network may vary with respect to their native operating systems and internal representation of numbers. Hetero Helix presents a simple shared memory programming model to developers, and considers the needs of designers, system integrators and maintainers. The key software technology in Hetero Helix is a compiler which automatically generates code for translating data representations from the format native to each machine into a common format and vice versa. The design of Hetero Helix was motivated by the requirements of robotics applications. >

DiSOM is a software-based distributed shared memory (DSM) system, which supports intra- and inter-application sharing in heterogeneous networks of microprocessor workstations. Unlike previous DSM systems, DiSOM provides fine-grained control over communication while retaining a simple shared memory model. It achieves this by using an update-based implementation of entry consistency, semaphores, remote object invocation, dynamic decomposition of objects and object-oriented language mechanisms. These techniques allow programmers to exploit application-specific knowledge to improve performance. A comparison between DiSOM and TreadMarks, a state-of-the-art DSM system, shows that on average DiSOM executes 33% faster and sends 69% fewer messages and 38% less data.

This paper presents a multiprocessor performance prediction methodology supported by experimental measurements, which predicts the execution time of large application programs on large parallel architectures based on a small set of sample data. We propose a graph model to describe application program behavior. Important and implicit architecture parameters are obtained by experiments. We focus on performance predictions of application programs on multiprocessors with implicit communications. A large scientific simulation program is implemented using the shared-memory model on the KSR-1 and using the data-parallel model on the CM-5 for performance measurements and prediction validation. We show that experimental measurements provide strong support for the performance prediction on multiprocessors with implicit communications and complex memory systems. >

This paper presents Proteus, an architecture-independent language suitable for prototyping parallel and distributed programs. Proteus is a high-level imperative notation based on sets and sequences with a single construct for the parallel composition of processes. Although a shared-memory model is the basis for communication between processes, this memory can be partitioned into shared and private variables. Parallel processes operate on individual copies of private variables, which are independently updated and may be merged into the shared state at specifiable barrier synchronization points. Several examples are given to illustrate how the various parallel programming models, such as synchronous data-parallelism and asynchronous control-parallelism, can be expressed in terms of this foundation. This common foundation allows prototypes to be tested, evolved and finally implemented through refinement techniques targeting specific architectures. >

Cluster of workstations or personal computers connected with high speed network has become one of major architectures of distributed memory parallel computers. However, software on the cluster environment is still not improved in performance. In particular, there has not been proposed a standard distributed shared memory mechanism on the cluster environment. The distributed shared memory can be a solution of programming style on distributed memory parallel system including clusters because we know from experiences that shared memory model makes programming easy. It must be implemented with care for the performance problem because we cannot assume any hardware support for shared memory system in the cluster environment. Another, but serious problem is the portability. In this paper, we discuss the design and implementation of portable distributed shared memory system. Our shared memory system is based on PVM in consideration of portability. Our contribution in this paper is the design and implementation of portable shared memory system on the cluster environment using faithful implementation of active messages fully in software, together with an enhancement of PVM to support active messages.

A Parallel Single Level Store systems (PSLS) integrates a shared virtual memory and a parallel file system. Managing globally the data, they provide programmers of scientific applications with the attractive shared memory programming model combined with a large and efficient file system in a cluster. In this paper, we present a cheap and efficient two-level checkpointi- ng approach enabling a PSLS to tolerate failures. The first level checkpointing algorithm is very efficient and saves data in memory but requires a large amount of memory space. When memories are saturated, an alternative algorithm, saving a checkpoint on disks is implemented. Performance results present the impact of different variants of the checkpointing algorithms.

OpenMP is a relatively new industry standard for programming parallel computers with a shared memory programming model. Given that clusters of workstations are a cost-effective solution for building parallel platforms, it would of course be highly interesting if the OpenMPmo del could be extended to these systems as well as to the standard shared memory architectures for which it was originally intended.

Principles for coordination and composition of parallel/distributed programs are discussed. We advocate a synchronizing shared memory model (EDA) for coordination and an algebraic approach to building programs using a linking language (LL) based on module composition, restriction and renaming. A prototype system ErlEda illustrating these principles is described. The system uses the concurrent programming language Erlang and its distributed environment as a basis. We illustrate the approach using the Dirichlet problem.

One of the keys for the success of parallel processing is the availability of high-level programming languages for on-the-shelf parallel architectures. Using explicit message passing models allows efficient executions. However, direct programming on these execution models does not give all benefits of high-level programming in terms of software productivity or portability. HPF avoids the need for explicit message passing but still suffers from low performance when the data accesses cannot be predicted with enough precision at compile-time. OpenMP is defined on a shared memory model. The use of a distributed shared memory (DSM) has been shown to facilitate high-level programming languages in terms of productivity and debugging. But the cost of managing the consistency of the distributed memories limits the performance. In this paper, we show that it is possible to control the consistency constraints on a DSM from compile-time analysis of the programs and so, to increase the efficiency of this execution model.

MPI/MBCF is a high-performance MPI library targeting a cluster of workstations connected by a commodity network. It is implemented with the Memory-Based Communication Facilities (MBCF), which provides software mechanisms for users to access remote task's memory space with off-the-shelf network hardware. MPI/MBCF uses Memory-Based FIFO for message buffering and Remote Write for communication without buffering from among the functions of MBCF. In this paper, we evaluate the performance of MPI/MBCF on a cluster of workstations with the NAS Parallel Benchmarks. We verify whether a message passing library implemented on the shared memory model achieves higher performance than that on the message passing model.

This paper presents conception of virtual shared files (VSF) as paradigm of parallel components interaction. Metaphor of virtual shared files space ensures a compromise between flexibility of explicit message passing and transparency of shared memory model. VSF are based on ordinary I/O notion and look like matrixes and ordinary files for application programmers. The most essential design issues are: all operations are applied to a file as a whole; operations remotely changing the content of file are prohibited; memory is explicitly allocated by user what is essential for massively-parallel computers.

In this article we concentrate on semantics of operations on synchronizing shared memory that provide useful primitives for shared memory access and update. The operations are a part of a new shared-memory programming model called mEDA. The main goal of this research is to provide a flexible, effective and relatively simple model of inter-process communication and synchronization via synchronizing shared memory.

The goal of the SISCI-Pthreads project is the implementation of a completely transparent, POSIX compliant thread package on top of clusters of PCs. This will not only allow users to run multithreaded applications on loosely coupled systems in the same way as on SMPs, but will also introduce the shared memory programming model in an unrestricted fashion to clusters of PCs. Hence, porting efforts of existing multi-threaded applications will be reduced and this new architecture will be opened to a wide variety of new applications and users. In order to achieve this complete transparency in an efficient manner, this effort is based on a new interconnection technology, the Scalable Coherent Interface (SCI), which allows remote memory accesses in a cluster environment by providing a global physical address space.

This paper describes an efficient implementation of MPI on the Memory-Based Communication Facilities; Memory-Based FIFO is used for buffering by the library, and Remote Write for communication with no buffering. The Memory-Based Communication Facilities are software-based communication mechanisms, with off-the-shelf Ethernet hardware. They provide low-cost and highly-functional primitives for remote memory accesses.

Cluster of workstation or personal computers connected with high speed network has become one of major architectures of distributed memory parallel computers. However, software on the cluster environment is still not improved in performance. The distributed shared memory can be a solution of programming style on distributed memory parallel system including clusters because we know from experiences that shared memory model ease programming. However, it must be implemented with care for the performance problem where there is no hardware support for shared memory system. Another, but serious problem is the portability. In this paper, we discuss the design and implementation of portable distributed shared memory system. Our shared memory system is based on PVM in consideration of portability. Our contributions in this paper is the design and implementation of portable shared memory system on the cluster environment using faithful implementation of active messages fully in software, together with an enhancement of PVM to support active messages.

We present a deterministic leader election protocol that can tolerate up to n−1 undetectable initial failures, where n is the number of processes. We assume an asynchronous shared memory model that supports only single writer and multi readers regular registers