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An efficient procedure is proposed for computing the N-point (N = 2[superscript n]) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. A DCT architecture is proposed that does not requre scale factor compensation.

An efficient pipelined architecture is proposed for the N [superscript m]-point m-dimensional discrete Fourier transform (DFT).

A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and the BCD-4221/5211 code. The signed-digit radix-10 recoding is used to recode the BCD multiplier to the digit set [-5, 5] from [0, 9]. The redundant BCD XS-3 code is adopted to generate the multiplicand multiples in a carry-free manner. The XS-3 coded partial products (PPs) are converted to ODDS PPs to fit binary partial product reduction (PPR). In this paper, a regular decimal PPR tree using ODDS and BCD-4221/5211 codes is proposed; it consists of a binary PPR tree block, a non-fixed size BCD-4221 counter block and a BCD-4221/5211 PPR tree block. The decimal carry-save algorithm based on BCD-4221/5211 is used in the PPR tree to obtain high performance multipliers. Moreover, an improved PPG circuit and an improved parallel prefix/carry-select decimal adder are proposed to further improve the performance of the proposed multipliers. Analysis and comparison using the 45 nm technology show that the proposed decimal multipliers are faster and require less hardware area than previous designs found in the technical literature. [ABSTRACT FROM PUBLISHER]

Discusses the historial development of computers from electronic calculators to current pocket-sized devices. [ABSTRACT FROM PUBLISHER]

A novel algorithm that uses a multidimensional systolic array is proposed to implement the multidimensional discrete Fourier transform. In addition, extensions of the multidimensional systolic array that is applicable for fast Fourier transform calculations are presented. The proposed algorithm combines two unique types of semisystolic arrays into a single systolic array that accepts streams of input data produced at the boundary of the array.