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NbN RSFQ circuits operating at 9 K reduce the cooling constraints especially for portable, remote, telecoms or medical imaging applications. We have developed a test-bed to study the operating temperature of the various mixed RF and digital circuit blocks of NbN `HyperSCAN' project test vehicle 1 cm2 chips. The use of a widespread helium cryostat (`Orange-ILL') allows us to stabilize the chip temperature in the range 2.9 K-20 K with thermal oscillations lower than 0.1 K. The chip is mounted on a PCB and shielded from the external field: the PCB provides a multi-connection packaging used in order to study temperature and frequency operation of 30 GHz NbTiN CPW filters, RSFQ gates, analog SQUID and NbN/TaN/NbN SNS junctions arrays. The comparison between electrical simulations and tests is made on flexible, ~ 56 cm long, micro-strip line ribbon cable carrying 32 signals each including bias lines, in the range of DC-3 GHz, combined with 4 semi-rigid ~ 40 GHz coaxial cables. By removing spurious resonances, it is expected to take full benefit of the large bandwidth, low insertion loss and low thermal conductivity of the set-up. We emphasis on the flexibility, large yield, reliability and reduced cost of such packaging coupled to He cooling exchanger for applying to testers and to future 9 K NbN multi-ADC green and remote systems when only low electrical power sources are available.

NbN-TaN-Nb(Ti)N non-hysteretic SNS Josephson junctions with TaXN barriers tuned through nitrogen content at metal-insulator transition have been produced in a reliable way with characteristic voltage RNIC above 1.5 mV at 9 K. Barriers are typically 7-10 nm thick and Jc in the range 5 to 25 kA/cm-2 making feasible LSI RSFQ ADC circuit integration by using the lithographic tools of the Leti C-MOS platform. Junction tri-layers, NbTiN ground-plane and wiring levels have been reactively sputtered and optimized at 300°C in a reproducible way on 8-inch oxidized silicon wafers. A deep UV stepper combined with SF6 gas mixtures RIE has been used to achieve low spread lithography in junction diameters of 716 nm (3σ ~ 40 nm), of 465 nm (3σ ~ 84 nm) across the 8-inch. A well controlled CMP planarization process has been developed on thick PE-CVD silica layers deposited on each superconducting nitride layer. On-line FIB-SEM observations and electrical characterizations associated to the development of a technology test vehicle demonstrate the feasibility of the complete process. The reliable production of nitrides LSI RSFQ circuits such as ADCs and integrated imagers operating in a relaxed cryogenic environment in the 6-10 K temperature range is foreseen to open new telecoms and medical applications. Moreover, a new MgO-AlN-MgO layered insulating barrier junction is shown to operate above 10 K and will be developed for analog front-end circuit parts.

A detailed investigation of tunneling has been carried out on Nb-Nb 2 O 5 -Pb(In) junctions where the tunnel barrier is made-of Nb 2 O 5 thermal oxide with accurately controlled oxidation parameters. The oxide barrier appears as a n-type semiconductor with two Schottky barriers at the interfaces. The transport of charged oxygen vacancies is supposed to play a fundamental role in the oxidation process. The barrier potential φ and the tunnel resistance R have been related to the oxidation parameters. The junctions realized have sizes ranging from 4 to 104μm2, the Josephson current density, dependent on the oxide thickness, is in the 1-105A/cm2range. Very low transition times from the superconductive to the normal state have been observed.