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This article presents a carrier phase shifting technique for minimizing the aggregate harmonics in networks of asymmetric parallel-connected inverters for distributed power generation system applications. The proposed technique is: 1) implemented in a decentralized manner, relying only on local voltage and current measurements, and 2) optimal in the sense that it minimizes a cost function representing the carrier-frequency current harmonics. The analysis indicates that the proposed optimal carrier phase shifting technique can enable order-of-magnitude reductions in harmonic power, and also universal improvements compared to symmetric carrier interleaving for asymmetric inverter networks. Moreover, compared to existing methods that require either centralized communication or information exchange between inverters to coordinate carriers, the proposed technique is completely decentralized, which provides important practical benefits for implementation, including improved robustness and reduced cost. The technique is experimentally validated on a network of three single-phase 2-kW inverters and demonstrates a 36.5% reduction in the weighted total harmonic distortion factor of the aggregate inverter current, and the ability to converge to the optimal carrier phase spacing dynamically in less than one line frequency cycle (16.7 ms) in steady state and transient operating conditions.

We present a decentralized control strategy that yields switch interleaving for parallel-connected dc–dc buck converters. Compared to state-of-the-art methods that are distributed at best, the proposed architecture requires no communication, and hence, presents a variety of advantages with regard to reliability, modularity, and cost. The method is based on the digital implementation of the dynamics of a Lienard-type oscillator circuit as the controller for the converters. Each controller only requires the locally measured output current to synthesize the pulsewidth modulation (PWM) carrier waveform. The intrinsic electrical coupling between converters drives the nonlinear-oscillator-based controllers to converge to an interleaved state with uniform phase spacing across PWM carriers, independent of the number of converters, the load, and initial conditions. We provide analytical guarantees for existence and stability of the interleaved state as well as extensive hardware results for a system of five 120 W 48 V-to-12 V dc–dc buck converters that demonstrate convergence to the interleaved state in the face of a variety of large-signal disturbances.

This paper presents a hybrid analog/digital computing circuit that solves a form of the selective harmonic minimization problem in a fast and scalable manner. Voltages in the circuit represent variables in the optimization problem, and, in steady state, converge to the optimal solution of the problem. A digital microcontroller sets voltages at particular nodes in the circuit as to program the cost function and other inputs to the optimization. We present a specific realization of the computing circuit that solves for eight independent switching angles for a quarter-wave symmetric PWM driven two-level single-phase inverter. This realization minimizes seven undesired harmonics while also maintaining control of the modulation index. The simulation results demonstrate that the proposed circuit can converge to the optimal solution in less than 5.0 ms. Our survey of prior methods indicates that this is substantially faster than existing published methods in the literature.

This paper presents the design, implementation, and experimental validation of a method for fault prognosis for power electronics systems using an adaptive parameter identification approach. The adaptive parameter identifier uses a generalized gradient descent algorithm to compute real-time estimates of system parameters (e.g., capacitance, inductance, parasitic resistance) in arbitrary switching power electronics systems. These estimates can be used to monitor the overall health of a power electronics system and to predict when faults are more likely to occur. Moreover, the estimates can be used to tune control loops that rely on the system parameter values. The parameter identification algorithm is general in that it can be applied to a broad class of systems based on switching power converters. We present a real-time experimental validation of the proposed fault prognosis method on a 3 kW solar photovoltaic interleaved boost dc–dc converter system for tracking changes in passive component values. The proposed fault prognosis method enables a flexible and scalable solution for condition monitoring and fault prediction in power electronics systems.

This paper introduces the notion of minimum distortion point tracking (MDPT): a control paradigm for input- or output-parallel connected dc-dc converters where switching waveforms are optimally phase shifted to minimize the total dc-bus ripple power. In a sense, MDPT generalizes the ubiquitous concept of interleaving in balanced multiphase dc-dc converters to a broad class of asymmetric input- or output-parallel connected dc-dc converters. Realizing power-quality improvement with control design implies that a drastic reduction in passive input or output filters can be achieved. This paper presents the mathematical characterization of the minimum distortion point (MDP) and a technique for MDPT. An experimental case study for three 600 W dc-dc converters demonstrates a 3× reduction in the bus voltage ripple, convergence to a static MDP in 40 ms, and the ability to dynamically track a time-varying MDP.

The paper presents the theoretical analysis, practical design considerations, and experimental verification of an improved robust adaptive parameter identifier for dc-dc power electronic converters. The proposed method improves the performance of a conventional linear switched adaptive parameter identifier by designing the observer gain using performance criteria. The design approach ensures the optimality of the observer gain as well as provides a degree of robustness to measurement noise and circuit non-idealities. We develop the design methodology for the robust adaptive parameter identifier and present experimental results that validate the achievable improvement in real-time parameter identification. The results indicate wide parameter tracking ranges (10% to 66% parameter deviations) and sub-second convergence, exceeding the performance of classically designed adaptive parameter identifiers.

This paper presents the design and experimental demonstration of a method for photovoltaic condition monitoring and hot-spot detection using a real-time adaptive parameter identification approach. The identification algorithm tracks parameters in an equivalent ac circuit model of a PV panel, and uses these parameter estimates to predict when the PV panel is partially shaded or in a hot-spot condition. The proposed hot-spot detection method has low computational overhead and requires only passive electrical measurements at the terminal of the PV panel. We present simulation and experimental results that demonstrate the accuracy of the parameter identifier and its ability to detect partial shading in a 10 W monocrystalline silicon solar panel.

This paper presents the analysis and design of an adaptive parameter estimator for power electronics circuits. Adaptive parameter estimation has been demonstrated to be a useful technique for enabling novel controls, monitoring, and fault diagnosis techniques in power electronics systems. We present an analysis of factors that affect the performance, stability, and feasibility of a gradient-type parameter estimation, along with simulation and experimental results that validate the analysis. Moreover, we derive theoretical limits on the convergence speed of the parameter estimation and demonstrate design techniques to maximize this limit while maintaining the robustness of the estimation. The paper provides a comprehensive analysis and design process for adaptive estimation schemes as applied to systems of switching power converters.

We present a decentralized control strategy that yields switch interleaving among parallel-connected dc-dc buck converters. The proposed method is based on the digital implementation of the dynamics of a nonlinear oscillator circuit as the controller. Each controller is fully decentralized, i.e., it only requires the locally measured output current to synthesize the pulse width modulation (PWM) carrier waveform and no communication between different controllers is needed. By virtue of the intrinsic electrical coupling between converters, the nonlinear oscillator-based controllers converge to an interleaved state with uniform phase-spacing across PWM carriers. To the knowledge of the authors, this work presents the first fully decentralized strategy for switch interleaving in paralleled dc-dc buck converters.

This paper develops and experimentally demonstrates a new class of high-fidelity model-based fault detection and isolation filters for three-phase AC-DC power electronics systems. The structure of these filters is similar to that of a piecewise linear observer and in the absence of faults the filter residual converges to zero. On the other hand, whenever a fault occurs, by appropriately choosing the filter gain, the filter residual will exhibit certain geometric characteristics that allow the fault to be detected and, in certain cases, also isolated. Key advantages of these filters include fast detection of all possible component faults and the ability to capture slow degradation in individual components. In order to experimentally demonstrate their feasibility, the filters are implemented on an ultra-fast application-specific real-time processor. While the theoretical framework developed is general, the analysis, simulations, and experiments are focused on widely used power electronics systems implementing three-phase AC-DC converters that are used in, e.g., motor drive applications and distributed static compensators.

This paper presents an approach for nominally lossless regulation of the output voltage, and for design of tight closed-loop voltage control of a resonant switched-capacitor (ResSC) dc-dc converter. A switching pattern for the ResSC dc-dc converter that enables wide range lossless voltage regulation and zero voltage switching (ZVS) is developed. An appropriate small signal model is derived based on the generalized averaging method. In view of the dynamics of the developed small signal transfer functions, a compensation method based on a minor phase loop is introduced to stabilize the system. The steady state and transient responses of the system are evaluated based on the developed model. The performance of the proposed controller is verified by a switch-based simulation in a design example for on-chip power delivery application.

We describe the design, implementation, and experimental validation of an ultra-fast real-time hardware-in-the-loop emulation of a permanent magnet synchronous machine (PMSM) inverter drive. The power electronics converter and machine are modeled using a flexible piecewise linear state space approach and are simulated in hard real-time with 1 μs time step, which enables high-fidelity modeling of converter switching dynamics, including dead time and fully rectifying mode. We validate the fidelity of the real-time PMSM drive emulation by making real-time comparisons with a reference hardware model of a PMSM drive (scaled down system rated at 2.7 A and 200 V). Additionally, we experimentally demonstrate the capability of the hardware-in-the-loop PMSM drive emulation under various operating scenarios, including steady state, transient, and fault conditions.

In this paper, we describe the design and implementation of a state observer for power electronics converters, the dynamics of which can be described by a linear-switched state-space model. The observer is also described by a linear-switched state-space model, and for each particular subsystem, the observer essentially behaves as a Luenberger observer. As part of the design procedure, we provide sufficient conditions that guarantee the stability of the observer. In order to experimentally demonstrate its feasibility, the observer is implemented in a dedicated real-time processor architecture. We present experimental results that illustrate the observer behavior when used for state estimation in single-phase and two-phase boost converters.