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This paper presents a novel organic embedded trace damascene redistribution layer (RDL) process for panel-scale 2.5-D interposers and high-density fan-out package (HDFO) substrates. A minimum feature size of 1.5- \mu \textm line and space using ultrathin polymer dielectrics on glass, silicon, and as well as on organic laminate was demonstrated. This is the first demonstration of a complete set of materials and processes that can be applied to large glass or organic panels, to bridge the interconnect gap between current semiadditive process (SAP) RDL and wafer back-end-of-line (BEOL) RDL. The ultra-fine pitch multilayer RDL structures demonstrated in this paper achieve an optimum balance of high IO density, high electrical performance, and low process costs. IO density in terms of IOs per mm per layer, as defined by Intel, refers to the number of traces routed per millimeter of die edge on one RDL layer of an interposer or package substrate. The current SAP technology can achieve an IO density of about 40 IOs/mm/layer on 510 mm $\times \,\, 510$ mm organic laminate panels. The challenges of fabricating copper metal traces below 5 20~\mu \text{m} or less; 3) high AR of routing traces in the range of 2–4; 4) precise RDL linewidth control; 5) double-sided process with glass core; and 6) reduced number of process steps and panel-scalability leading to lower fabrication costs. [ABSTRACT FROM PUBLISHER]

This paper presents a multilayer wiring board that integrates a copper air-core microinductor to enable a highly compact, chip-scale power converter module. The wiring board is wafer-level fabricated with three 30-μm-thick electroplated copper layers and is subsequently detached from the fabrication wafer to yield a board that is only 90 μm thick for minimum overall module volume. Within this platform, a stacked-spiral air-core microinductor is designed for high-switching-frequency power conversion and yields high inductance density of 128 nH/mm 2 (100 nH/mm 3 by volume, including 600 μm clearances both above and below the inductor to minimize coupling with external conductors). Although this technology is anticipated to be more appropriate for emerging, experimental converters with switching frequencies >30 MHz, a proof-of-concept, ultraminiature (9 mm 2 footprint, 0.7 mm thick) power converter module is presented that utilizes the microinductor wiring board in conjunction with a commercially available surface-mount boost regulator (~4 MHz switching frequency). The converter module yielded a maximum output power of 153 mW at 60% efficiency for a volumetric power density of 24 mW/mm 3 based on the physical volume occupied by the module (13 mW/mm 3 based on the volume needing to be kept clear from external conductors). [ABSTRACT FROM AUTHOR]

Highlights: [•] Copper deposition mechanism is stated and mathematical models of the Cu electroplating are established by a series of electrochemical equations. [•] Finite element models (FEM) are built to simulate two different kinds of copper electroplating processes in through-hole via. [•] Experiments show the feasibility of the Cu TSV fabrication under different conditions based on the simulation optimized results. [•] Defect-free Cu TSVs are successfully applied to the Wafer Level Packaging (WLP) Pirani vacuum gauges for the vacuum packaging of MEMS. The devices are proved to be robust and high accuracy. [ABSTRACT FROM AUTHOR]

Abstract: Anisotropic microstructure is becoming a critical issue in microbumps used in 3-D integrated circuit packaging. We report here an experimental approach for controlling the microstructure of η-Cu6Sn5 intermetallic compound in microbumps by using 〈111〉 oriented and nanotwinned Cu pads as the under-bump-metallization. By electroplating arrays of large numbers of 〈111〉 oriented and nanotwinned Cu pads and by electroplating the Sn2.3Ag solder on the pads, we form η-Cu6Sn5 in the reflow at 260°C for 1min. The η-Cu6Sn5 showed a highly preferential growth along the 〈0001〉 direction. As reflow time is extended, the preferred texture of η-Cu6Sn5 changed to { }. The results indicate that we can control the uniform microstructure of η-Cu6Sn5 intermetallic by controlling the microstructure of the Cu under-bump-metallization. [Copyright &y& Elsevier]

This paper evaluates field-based current sensing integration in power electronic modules. Point field detectors, such as giant magnetoresistor detectors, can provide high-bandwidth (dc to megahertz) current measurements with a small footprint (1.26 \mm^2). Magnetic fields surrounding a current-carrying conductor are frequency dependent, so the 5 \% flat-bandwidth metric is used to evaluate placement of the point field detectors to maximize the bandwidth of the current measurement. A significant contribution of this paper is an evaluation of the placement of point field detectors inside a power switching module. This paper focuses on detector placement for the interconnect structures commonly found in power switching modules. Experimental and finite-element analysis of wire bond structures with multiple wire bonds and lead frame structures are evaluated for high-bandwidth sensing performance. [ABSTRACT FROM PUBLISHER]

3-D technologies with stacked chips have the potential to provide new chip architecture, and improved device density, performance, efficiency, and bandwidth. The increased power density in 3-D technologies can become a daunting challenge for heat removal. Furthermore, power density can be highly nonuniform, leading to time- and space-varying hotspots, which can severely affect performance and reliability of integrated circuits. It is important to mitigate on-chip thermal gradients while considering the associated cooling costs. One efficient method of hotspot thermal management is to use superlattice thermoelectric coolers (TECs), which can provide on demand and localized cooling. In this paper, a detailed 3-D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is developed to investigate the efficacy of TECs in hotspot cooling for 3-D technology. A strong vertical coupling has been observed between TECs located in top and bottom dies. Bottom TECs can significantly heat the top hotspots in both steady-state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between TEC and heat spreader are shown to have a crucial effect on the TEC performance. We observe up to 5.6^\circC of active hotspot cooling in steady state and 7.4^\circC of active hotspot cooling using a square root current pulse. [ABSTRACT FROM PUBLISHER]

In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but to still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder microbumped chip is bonded on an Si wafer using chip-to-wafer bonding technique. Furthermore, the microgap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips without the underfill is measured and it exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, scanning acoustic tomography analysis, and cross-section with scanning electron microscopy analysis. The stacked ICs are evaluated by reliability (thermal cycling) test (-55 to 125°C). Finally, ultrafine-pitch (5-μm pads on a 10-μm pitch) lead-free solder microbumping is explored. [ABSTRACT FROM PUBLISHER]

In recent years, there has been growing demand to increase the power density in power modules. Therefore, the thermal management of power modules has become more and more critical. In this paper, we show that conventional single-sided power module with wire-bond connection cannot achieve both good steady-state and transient thermal performance under high heat transfer coefficient conditions. The plate-bonded power module has been proposed to resolve this issue. However, the thick copper plate embedded in the power module induces large thermomechanical stress during temperature cycling, leading to poor reliability. To reduce the thermomechanical stress without significantly compromising the thermal performance, a trenched copper plate power module is designed and presented. A parametric study shows that the maximum von Mises stress and plastic strain in the solder layer can be reduced by 18.7%, and 67.8%, respectively, if the single piece of copper plate is replaced by a 3 × 3 trenched copper plate. [ABSTRACT FROM PUBLISHER]

In thermosonic wire bonding, a free air ball (FAB) created by electronic flame-off (EFO) is crucial to a reliable first bond. To reveal the mechanisms of FAB and ripple formation, the dynamic FAB formation process was monitored and analyzed with a high-speed camera and digital data acquisition system. FAB formation was found to occur in four stages: initiation, preheating, melting, and solidification. The FAB formation speed and model depend only on the EFO current. The FAB formation speed can be as high as 90.4 μm/ms at an EFO current of 60 mA. A minimum EFO time is required for FAB formation, which depends on the EFO current. A semiempirical model FAB=ηln[I(t - 0.5 tmin)]- c, was developed to describe the relationship between the FAB size and the EFO time at different EFO currents. The ripple formation mechanism was investigated by analyzing the solidification stage images. Transient droplet vibration caused by high-speed rolling-up and skin-forming solidification in the molten gold drop caused by a large temperature gradient are two major factors in ripple formation. This analysis is expected to be useful for understanding the FAB formation mechanism and optimizing the EFO parameters. [ABSTRACT FROM PUBLISHER]

This paper focused on the feasibility of preparing Sn-Ag-In ternary solder bumps with small size by two-step electroplating. The interfacial reaction and shear strength between three different solders (Sn2.2Ag, Sn1.8Ag9.4In, and Sn1.6Ag21.7In) and Cu under bump metallization (UBM) were investigated. After the reflow for 10 min, η Cu6(Sn,In)5 and ε Cu3(Sn,In) intermetallic compounds (IMC) were formed at the interface near the solder matrix and Cu UBM, respectively. Indium addition lowered the reflow temperature and improved the interface between solder and IMCs. The mean shear strength of Sn1.8Ag9.4In solder bump was higher than that of Sn2.2Ag and Sn1.6Ag21.7In solder bumps. After long time reflow, the mean shear strength increased. [ABSTRACT FROM PUBLISHER]

This paper discusses the optimization of a stretchable electrical interconnection between integrated circuits in terms of stretchability and fatigue lifetime. The interconnection is based on Cu stripes embedded in a polyimide-enhanced (PI-enhanced) layer. Design-of-experiment (DOE) methods and finite-element modeling were used to obtain an optimal design and to define design guidelines, concerning both stripe and layer dimensions and material selection. Stretchable interconnects with a PI-enhanced layer were fabricated based on the optimized design parameters and tested. In situ experimental observations did validate the optimal design. Statistical analysis indicated that the PI width plays the most important role among the different design parameters. By increasing the PI width, the plastic strain in the Cu stripes is reduced, and thus, the stretchability and fatigue lifetime of the system is increased. The experimental results demonstrate that the PI-enhanced stretchable interconnect enables elongations up to 250% without Cu rupture. This maximum elongation is two times larger than the one in samples without PI enhancement refid="ref1"/ . Moreover, the fatigue life at 30% elongation is 470 times higher refid="ref2" . [ABSTRACT FROM PUBLISHER]

In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn micro-bump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 \mum. The actual TSV and micro-bump process uses 3 masks, two Si-deep-reactive ion etching steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 \mum∼\emptysetTSV, 5 \mum thick polymer liner, 25-\mum\-\emptyset Cu TSV, 50 \mum deep TSV, and a 60 \mum TSV pitch. [ABSTRACT FROM AUTHOR]

An Ag spot/full nickel and nickel phosphorus (NiNiP)-plated Cu leadframe without the anti-tarnish layer was used for aluminum wire bonding in power packages. Two periods of shelf-life, namely 7 months and 13 months, of the leadframe were studied in terms of processability (die attachment and wire bonding) and package reliability. It was found that the leadframe with 7-month shelf-life showed positive results for both processability and package reliability. The leadframe with 13-month shelf-life showed positive results for processability. However, it showed delamination at the leads between the NiNiP leadframe surface and the molding compound interface after high-temperature storage for 1000 h. Further analysis showed that the delamination is related to Ni diffusion into the interface of the NiP/molding compound and S in the molding compound during the reliability test. [ABSTRACT FROM PUBLISHER]

A 3-D solid-state drive system with through-silicon via (TSV) technology and boost converter is presented in this paper. The proposed boost converter enables the supply voltage reduction to 1.8 V and smaller NAND Flash memory chips. From the simulation results, the conventional bonding-wire technology can achieve only eight NAND chip integrations not only due to their structural problem but also due to the performance degradation. On the other hand, 128 NAND Flash memory chips can be integrated into a package with full-copper TSVs and the proposed system has about 1.70 \mus of rise time for 20 V, 74.2 nJ of the energy dissipation, and 225 \mum^2 of additional Si area consumption for a NAND chip. Even if poly-Si TSVs are used, because of the process restriction, 64 NAND chips can be stacked with about 34% longer rise time and 22% degradation of energy dissipation compared to a full-copper TSV by grinding the Si-substrate to 10 \mum. [ABSTRACT FROM PUBLISHER]

Double-sided power modules are particularly attractive due to their high thermal performance. Thanks to the stacking of two direct bond coppers, very low stray inductances may be expected, particularly because of the proximity of the two rear metalizations. On the other hand, capacitive effects may be increased. In this paper, the complete electromagnetic behavior of double-sided power modules is studied, regarding both internal coupling and unwanted electromagnetic compatibility emissions. Some layout and active solutions are proposed to reduce common-mode emissions. [ABSTRACT FROM AUTHOR]

High-Q copper inductors were fabricated on low-cost and low-loss bismaleimide triazine (BT) and glass substrate using electroplating process. A differential LC voltage-controlled oscillator (VCO) circuit was designed using these high-Q inductors at 2.4 GHz. Flip chip and multichip module (MCM) technologies were applied to assemble the active chips on BT and glass substrate. The inductors exhibited Q-factor as high as 25 at 2.4 GHz. VCOs with copper inductors on BT and glass substrate had phase noise of-108 dBc/Hz at 600 kHz offset for a 2.4-GHz carrier, which is 6-dB improvement compared with the one with on-chip Al inductors. There was almost no substrate loss for inductors on BT and glass substrates. The effect of fabrication defect and solder joint resistance were also investigated. This technique can be extended to other building blocks, thus realizing integration of the whole RF system. [ABSTRACT FROM AUTHOR]