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Summary: In this paper, a technique is proposed to improve the jitter performance of a delay‐locked loop (DLL). The DLL is structured by charge pump (CP), phase detector (PD), voltage control delay line (VCDL) and the reference clock. The jitter generated by each part of DLL is separately studied, and a closed‐form equation is extracted. This closed‐form equation shows that the jitter generated by CP, PD and the secondary jitter of the reference clock and VCDL is applied to output by the control voltage. A jitter improving circuit is used to cancel the jitter of the control voltage. To verify the closed‐form equation, the DLL is designed in 0.18 μm CMOS technology with the proposed technique to improve the output jitter. The simulated root‐mean‐square and peak‐to‐peak jitters are 2.12 and 4.37 ps at 250 MHz, respectively. The power dissipation at 250 MHz is 2.78 mW for a supply voltage of 1.2 V. [ABSTRACT FROM AUTHOR]

This paper presents a time-domain model for general jitter analysis of delay-locked loops (DLLs). According to this model, the noise contribution of each part of the circuit is specified at the output of DLL, and a closed-form relationship is extracted. By this closed-form relationship, we show that accumulated jitter, known as jitter peaking, always exists due to the loop filter capacitor in a widely used DLL configuration. The effect of jitter accumulation can cause an unstable lock state. A conventional DLL is simulated in 0.18 µm CMOS technology to verify the closed-form relationship. [ABSTRACT FROM AUTHOR]