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Optical network-on-chip (ONoC) is an emerging upgrade for electronic network-on-chip (ENoC). As a kind of ONoC, wavelength-routed ONoC (WRONoC) shows ultrahigh bandwidth and ultralow latency in data communication. Manually designed WRONoC topologies typically reserve all to all links. This causes the waste of resources. Topology customization for each individual communication network can save resources, but requires automation for efficient design. The state-of-the-art design automation method is not efficient and does not support crosstalk analysis and signal-to-noise ratio (SNR) optimization. Moreover, the state of the art does not consider the physical locations of the data sending/receiving ports, causing unavoidable detours and crossings in the physical layout. In this work, we present FAST+: an automatic topology customization and optimization method. Compared with the state of the art, FAST+ operates much more efficiently and proposes a concrete router-level crosstalk-analysis method and a novel SNR optimization algorithm. This work also provides solutions to avoid detours and crossings in the physical layout. When SNR optimization is not enabled, experimental results show that FAST+ runs thousands times faster than the state of the art on average while providing multiple better or equally good topologies regarding resource usage and the worst case insertion loss. When SNR optimization is enabled, FAST+ provides $1.75\times $ better worst case SNR on average after the optimization while not sacrificing resource usage and the worst case insertion loss. [ABSTRACT FROM AUTHOR]

Length-matching is an important technique to balance delays of bus signals in high-performance printed circuit board (PCB) routing. Existing routers, however, may generate very dense meander segments. Signals propagating along these meander segments exhibit a speedup effect due to crosstalk between the segments of the same wire, thus leading to mismatch of arrival times even under the same physical wire length. In this paper, we present a post-processing method to enlarge the width and the distance of meander segments and hence distribute them more evenly on the board so that crosstalk can be reduced. In the proposed framework, we model the sharing of available routing areas after removing dense meander segments from the initial routing, as well as the generation of relaxed meander segments and their groups for wire length compensation. This model is transformed into an ILP problem and solved for a balanced distribution of wire patterns. In addition, we adjust the locations of long wire segments according to wire priorities to swap free spaces toward critical wires that need much length compensation. To reduce the problem space of the ILP model, we also introduce a progressive fixing technique so that wire patterns are grown gradually from the edge of the routing toward the center area. Experimental results show that the proposed method can expand meander segments significantly even under very tight area constraints, so that the speedup effect can be alleviated effectively in high-performance PCB designs. [ABSTRACT FROM PUBLISHER]