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This article presents a multilayer graphene nanoribbon (MLGNR)‐based single‐tier on‐chip nanoscale via‐interconnect scheme (VIS), which combines the vertical MLGNR via and horizontal MLGNR interconnect, as a prospect for monolithic 3D (M‐3D) integrated circuits (ICs). To go beyond the simplifying assumptions of perfect MLGNR and conventional skin‐effect, this study incorporates the impact of edge‐ and substrate‐induced scatterers in a realistic MLGNR and considers the 1D skin depth formula for MLGNR‐based on‐chip interconnect and via. A combined equivalent circuit model is developed to analyze the challenges induced by scatterers, skin‐effect, and crosstalk effect in perfect MLGNR VIS (P‐VIS) and realistic MLGNR VIS (R‐VIS). The results show that for width in the range of 5–30 nm, P‐VIS outperforms R‐VIS in terms of crosstalk delay. Moreover, at high frequencies ranging from 1 to 104 GHz with a width of 16 nm, R‐VIS demonstrates a performance decline of 243.18% (5.3934 × 103%) for L = 4.8 μm (1 mm), respectively, in comparison with P‐VIS. Hence, in order to leverage the potential of MLGNR‐based VIS for M‐3D ICs at high frequencies, it is imperative to integrate Li‐intercalation doping and mitigate the impact of edge and substrate scatterers in MLGNR. [ABSTRACT FROM AUTHOR]

Network on chip (NoC) is the main solution to the communication bandwidth of a multi-processor system on chip (MPSoC). NoC also brings more route requirements and is highly prone to errors caused by crosstalk. Crosstalk has become a major design problem in deep-submicron NoC communication design. Hence, a crosstalk error model and corresponding reliable system with error correction code (ECC) are required to make NoC communication reliable. In this paper, a reliability system evaluation model (RSE) of NoC communication with analysis from backend to frontend has been proposed. In the backend, a crosstalk error rate model (CER) is established with a three-wire RLC coupling model and timing constraints. The CER is used to establish functional relations between interconnect spacing, length and signal frequency, and test system reliability. In the frontend, a reliability system performance model (RSP) is established with a CER, reliability method cost and bandwidth. The RSE summarizes the frontend and backend model. In order to verify the RSE model, we propose a reliability system with a hybrid automatic repeat request technique (RSHARQ). Simulation demonstrates that the CER model is close to real circuit design. Through the CER and RSP model, the performance of RSHARQ could be simulated. [ABSTRACT FROM AUTHOR]

Transient analysis, limited by the variability of process-induced physical and geometrical parameters in the capacitively coupled Li-doped MLGNR interconnects operating at the subthreshold mode, is the subject of this paper. An analytical approach based on transmission-line theory is presented here to model crosstalk-induced noise in the subthreshold regime of capacitively coupled MLGNR interconnects. The effect of the underlying dielectric material's surface roughness on the performance characteristics of MLGNR interconnects is examined by deriving an equivalent mean free path (MFP) that accounts for surface roughness scatterings. Moreover, in order to understand the variability effect of MLGNR on-chip interconnects, the impact of the process-induced physical parameters (temperature and Fermi energy levels) and geometric parameters (dielectric thickness, interconnect length, and width) is being investigated. As temperature or interconnect length increases, crosstalk-induced delay (XTID) increases, while XTID decreases with increased fermi energy level, dielectric thickness, and width. It is worthwhile noting that the average error values obtained are not greater than 5% and 18% for the obtained Vmax and Vtime-duration, respectively. [ABSTRACT FROM AUTHOR]

Network on chip (NoC) is the main solution to the communication bandwidth of a multi-processor system on chip (MPSoC). NoC also brings more route requirements and is highly prone to errors caused by crosstalk. Crosstalk has become a major design problem in deep-submicron NoC communication design. Hence, a crosstalk error model and corresponding reliable system with error correction code (ECC) are required to make NoC communication reliable. In this paper, a reliability system evaluation model (RSE) of NoC communication with analysis from backend to frontend has been proposed. In the backend, a crosstalk error rate model (CER) is established with a three-wire RLC coupling model and timing constraints. The CER is used to establish functional relations between interconnect spacing, length and signal frequency, and test system reliability. In the frontend, a reliability system performance model (RSP) is established with a CER, reliability method cost and bandwidth. The RSE summarizes the frontend and backend model. In order to verify the RSE model, we propose a reliability system with a hybrid automatic repeat request technique (RSHARQ). Simulation demonstrates that the CER model is close to real circuit design. Through the CER and RSP model, the performance of RSHARQ could be simulated.

The present work explores the temperature-dependent performance evaluation due to crosstalk in coupled interconnects of intercalation-doped multilayer graphene nanoribbons (ID-MLGNR). A temperature-dependent equivalent single conductor (ESC) model of arsenic pentafluoride (AsF5) ID-MLGNR is considered and is employed to analyze its crosstalk performance (i.e., crosstalk-induced noise and crosstalk-induced delay). Other metallic interconnect materials viz. mixed carbon nanotube bundles (MCB) and copper (Cu) are also analyzed in a similar manner. The temperature-dependent crosstalk performance of ID-MLGNR is compared with that of MCB and Cu, at different temperatures from 300 to 500 K. For the specified temperature range, in case of crosstalk-induced noise, the AsF5 ID-MLGNR-based long interconnects demonstrate superior performance to its MCBs and Cu counterparts. Moreover, the temperature-dependent crosstalk-induced delay is less with ID-MLGNR in comparison with both MCB and Cu interconnects. The large values of the mean free path (MFP) and conductivity of AsF5 ID-MLGNR contribute to its improved performance. In addition, the impact of variation in MFP, interlayer spacing and Fermi level is studied on the crosstalk delay performance of ID-MLGNR. From the obtained results, it is revealed that variation in these parameters results in the significant variation of 62 ps, 51 ps and 169 ps, respectively, in the odd mode (OM) crosstalk delay. Hence, for emerging nano-technology nodes (e.g., 14 nm), ID-MLGNR interconnects with its improved crosstalk performance are proposed as a potential alternative to its MCBs and Cu counterparts. [ABSTRACT FROM AUTHOR]

This research paper presents a novel approach to analyze the crosstalk-induced delay of multi-layered graphene nanoribbon (MLGNR) and multi-walled carbon nanotube (MWCNT) interconnects. A multi-line driver-interconnect-load (DIL) system is employed to analyze the crosstalk-induced delay for different switching transitions. The interconnect lines of the proposed DIL are said to be operated by either a resistive or a CMOS, or a CNFET driver for different switching transitions at 32-nm technology. Using the unique CNFET driver, the victim line of the multi-level MLGNR/MWCNT-based bus system experiences a delay almost 57.25% and 31.62% lesser in comparison to a resistive driver and a CMOS interconnect driver, respectively. Additionally, the overall worst-case delays are reduced by 89.45% and 98.98% for MLGNR in comparison to an equivalent MWCNT at 100 μ m and 1,000 μ m interconnect lengths, respectively. [ABSTRACT FROM AUTHOR]

Boron nitride (BN) multi-layers are proposed as dielectric material for both horizontal and vertical graphene nanoribbon interconnects. The layer number dependence of the out-of-plane dielectric constant of BN multi-layers is utilized to simultaneously reduce the interlayer dielectric thickness and the crosstalk delay at 7 nm CMOS technology node. Since crosstalk effects are manifested more strongly in denser interconnects, the proposed all-two-dimensional-materials-based interconnection schemes are compared with Cu/low-k technology in terms of crosstalk delay. Results show that by reducing the interlayer dielectric thickness from 20 nm to 2 nm, the crosstalk delay ratio of the horizontal and vertical graphene nanoribbon interconnects to the Cu/pSiCOH counterparts decreases by 27.06% and 12.86%, respectively. It is also shown that as the interconnect length increases, both horizontal and vertical graphene nanoribbon interconnects with the BN dielectric prove more advantageous than the Cu/low-k counterparts. [ABSTRACT FROM AUTHOR]

This paper proposes novel triangular cross-sectioned geometry of carbon nanotube (CNT) bundles for crosstalk and delay reduction in CNT bundle interconnects for VLSI circuits. First, we formulate the equivalent single conductor (ESC) transmission line models of the interconnects. Through SPICE analysis of the ESC circuits, we find the propagation delays of the proposed CNT bundles. Next, we model the capacitively coupled interconnects for crosstalk analysis. It is found that the coupling capacitance of triangular CNT bundle is 29% lesser than the traditionally used square CNT bundles. Further, the crosstalk-induced delay of triangular interconnects is found to be 30% lesser when compared to square bundle interconnects. The reduction in delay is found to increase as the number of CNTs in the bundle increases. So, we suggest that triangular CNT bundles are the most suitable candidates as global interconnects. [ABSTRACT FROM AUTHOR]

In this paper, the crosstalk effects in multilayer graphene nanoribbon (MLGNR) interconnects are evaluated and are compared with those in multiwalled carbon nanotube (MWCNT) interconnects in ternary integrated circuits at the 10 and 7 nm technologies. For a more precise evaluation, the five-line bus architecture is considered. Furthermore, the effects of the top and bottom aggressors are considered for a more accurate analysis in sub-10 nm dimensions. The active and passive shielding techniques are also applied to reduce the crosstalk effects. Our results indicate that the MLGNR interconnects outperform the MWCNTs, especially in the more realistic seven-line case, which also considers the effects of the bottom and top layer aggressors. Also, the advantages of the MLGNR interconnects become more significant when the node shrinks from 10 to 7 nm. The crosstalk delays of normal, passively shielded, and actively shielded five-line MLGNRs at 7 nm are on average 49%, 56%, and 54% lower compared to their MWCNT counterparts, respectively. These improvements are 36%, 36%, and 41% regarding the power. Moreover, the normal and actively shielded MLGNRs have 25% and 72% smaller crosstalk noise area than their MWCNT counterparts, respectively. The smaller crosstalk noise for MLGNR leads to noise-free signals at the end of both actively and passively shielded victim lines in ternary logic at the 10 and 7 nm technologies. [ABSTRACT FROM AUTHOR]

Triangular carbon nanotube (T-CNT) bundles are proposed as long interconnects for subthreshold VLSI circuits. The performance of subthreshold interconnects depends on the intrinsic quantum and electrostatic coupling capacitances of the interconnects. Proposed T-CNT bundles have the most optimum geometry that give least possible coupling capacitance between adjacent wires in an IC. First, we describe the T-CNT bundle models and of traditionally used square/rectangular CNT bundles for comparison. The subthreshold output current of an inverter is modelled, and hence, we find the optimum transistor widths for nFET and pFET that drives the subthreshold interconnects. This is carried out by the current-over-capacitance ratio approach, where the subthreshold current and the transistor output capacitance are considered. Then, we model the interconnects using equivalent single conductor models and find their propagation delay and power dissipated. The performance factors such as crosstalk-induced delay, power delay product and victim noise levels of capacitive coupled interconnects of T-CNT bundles are compared to traditionally used square/rectangular CNT bundles for lengths ranging from 500 μm to 2000 μm. We find that T-CNT bundles outperform square/rectangular CNT bundles. [ABSTRACT FROM AUTHOR]

Rapidly increasing demand for higher data bandwidths has motivated exploration of new communication channels based on spatially multiplexed in-fibre and on-chip coupled light guides. However, the conventionally used periodically arranged coupled waveguides display complicated light propagation patterns, ranging from quasiperiodic to nearly chaotic. Taking a different approach, we spectrally engineer interwaveguide coupling to instigate self-imaging of the input light state at the array output and thus enable construction of novel high-fidelity interconnects. Simple implementation via modulation of the interwaveguide separations makes these interconnects realizable in all fabrication platforms. Their competitive advantages are negligible crosstalk-induced information loss, high density that exceeds the current standards by an order of magnitude, and compatibility with both classical and quantum information encoding schemes. Moreover, the wavelength-dependent self-imaging opens up new possibilities for wavelength and spatial division demultiplexing. The proposed analytical designs are supported by extensive numerical simulations of silicon-on-insulator, silicon nitride and silica glass waveguide arrays, and a statistical feasibility study. • Novel interconnects based on linearly coupled waveguide arrays. • High-fidelity information transfer without the crosstalk-induced loss. • An order of magnitude higher channel density than in conventional interconnects. • Inverse design applicable to the long-haul, short-range and on-chip interconnects. • Compatible with the standard modulation formats, classical and quantum encoding. [ABSTRACT FROM AUTHOR]

In order to analyse crosstalk delay and stability in single wall carbon nanotube bundle (SWCNT) interconnects, the time and frequency domain response are investigated in this paper. Based on the transmission line model and by using matrix formulation, we perform the Nyquist stability analysis to survey the dependence of the degree of relative stability for coupled SWCNT bundle interconnects. We present an exact transfer function formula for a SWCNT bundle and two coupled SWCNT bundle interconnects. The proposed model can be extended to coupled n bundled SWCNT interconnects. In order to demonstrate the crosstalk effects, we seek to compare the coupled SWCNT bundle interconnects with the SWCNT bundle interconnect. The results show that due to the capacitive and mutual inductive couplings between two SWCNT bundles, the stability of near-end output increases and the created undesirable voltage on the far-end output may reduce the stability and degrade logic. Also, it is observed that stability and switching delay of near-end output increases with increasing the interconnect length and diameter. Furthermore, maximum overshoot and switching delay of far-end output increases with length and diameter of interconnect. Also, as the parasitic coupling capacitance increases and the mutual inductance decreases, stability of near-end output increases whereas the stability of the far-end output decreases. Finally, compared to Advanced Design System results, the model exhibits an excellent accuracy. [ABSTRACT FROM AUTHOR]

Crosstalk effects in multilayer graphene nanoribbon (GNR) interconnects for the future nanoscale integrated circuits are investigated with the help of ABCD parameter matrix approach for intermediate- and global-level interconnects at 11nm and 8nm technology nodes. The worst-case crosstalk-induced delay and peak crosstalk noise voltages are derived for both neutral and doped zigzag GNR interconnects and compared to those of conventional copper interconnects. The worst-case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are less than 4% of that of copper interconnects for 1mm long intermediate interconnects and less than 7% of that of copper interconnects for 5mm long global interconnects at 8nm node. As far as the worst-case peak crosstalk noise voltage is concerned, neutral GNR interconnects are slightly better performing than their doped counterparts. But from the perspective of overall noise contribution, doped GNR interconnects outperform neutral ones for all the cases. Finally, our analysis shows that from the signal integrity perspective, perfectly specular, doped multilayer zigzag GNR interconnects are a suitable alternative to copper interconnects for the future-generation integrated circuit technology. [ABSTRACT FROM AUTHOR]

Current-mode signalling scheme is one of the prominent solutions for high-speed and high data rate communication in global on-chip interconnects. Advancements in nanofabrication processes and housing of billions of transistors on a single silicon chip have made process-induced variations in transistors and interconnects quite significant. Analysis of parameter variations has become an important step in predicting the reliability and addressing various electronic circuit design issues in nanoscale regimes. The present paper evaluates the stochastic parameters variability on the electrical performance of on-chip current-mode interconnect system. Both transistor and interconnect variability effects are analyzed. Interconnect is modelled by an equivalent distributed line model and is driven by a current-mode driver. The impact of variability is assessed via parametric, process corner and Monte–Carlo analyses. The variability analysis is carried out for single as well as coupled 2-Line, 3-Line and 5-Line interconnect structures. Furthermore, the impact of individual process parameter variability in current-mode interconnect system has been investigated using statistical techniques namely Taguchi design of simulation scheme, ANOVA and Rank table. [ABSTRACT FROM AUTHOR]

Crosstalk induced overshoot/undershoot effects in multilayer graphene nano ribbon interconnects (MLGNRs) are investigated with the help of ABCD parameter matrix approach for intermediate level interconnects at both 11 nm and 8 nm technology node. The worst case crosstalk induced peak overshoot voltage for perfectly specular, doped multilayer zigzag GNR interconnects is comparable to that of copper interconnects. The performance of neutral GNR interconnects is better than that of its doped counterpart with respect to peak crosstalk overshoot. But from the perspective of overall overshoot width and overshoot area contribution, perfectly specular, doped MLGNR interconnects outperform all other alternatives. As far as the effective electric field across the gate oxide is concerned, the doped MLGNR interconnects outperform neutral ones and copper interconnects for all the cases. It is estimated that the doped perfectly specular multilayer GNR interconnects have gate oxide failure rates ( AFR ) of ~ 240 × and ~ 790 × lesser than copper interconnects for 11 nm and 8 nm technology node respectively. So, from the gate oxide reliability perspective, perfectly specular, doped multilayer zigzag GNR interconnects are great advantageous to copper interconnects for the future integrated circuit technology generations. [ABSTRACT FROM AUTHOR]

We propose a formalism of a compact physical model for crosstalk noise analysis between two coplanar backward volume spin-wave interconnects. Comparing the amplitudes of the signal in the active line and the noise in the victim line, we introduce a figure of merit for crosstalk—the longitudinal or line-to-line coupling. It is shown that the crosstalk becomes prohibitively high as the edge-to-edge spacing between the lines goes down, and thus putting a limitation on the routing and placement in a spin-wave bus network. The position of the peak crosstalk noise coupling for different spacings and frequencies of excitation reveals a new limitation to the maximum interconnect length. Furthermore, the technique of superposition analogous to $RLC$ interconnects is exploited to explain the complicated nature of crosstalk noise and develop a mechanism for modeling crosstalk. Finally, a compact physical model is derived using analytical expressions, which demonstrate a reasonably good agreement with the actual full micromagnetic simulation results. [ABSTRACT FROM AUTHOR]

The temperature-dependent, crosstalk-induced, noise voltage waveform and its frequency spectrum, in capacitive coupled single-walled carbon nanotube (SWCNT) bundle interconnects, at the far end of victim line, have been analyzed at 22-nm technology node. A similar analysis is performed for copper interconnects and a comparison is made between the results of these two analyses. The SPICE simulation results reveal that at temperature variations ranging from 300 to 500 K, compared with conventional metal (copper) conductors, crosstalk noise voltage levels in CNT, at the far end of victim line, are significantly low. Simulated results further reveal that, with rise in interconnect temperatures, compared with copper interconnects, coupled interconnects of SWCNT bundle filter more noise frequency components. Based on these comparative results, an improved model for extracting inter-bundle, real life, coupling capacitances between SWCNT bundles has been proposed. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Purpose – This paper aims to reduce the worst-case crosstalk effects for resistance, inductance and capacitance (RLC) interconnects using the bus encoding technique. In current nanoscale technology, power dissipation, propagation delay and crosstalk performance of interconnects determine the overall performance of a chip. Signal integrity issues due to crosstalk in the form of voltage glitches, overshoots, undershoots, undesirable noise, propagation speed ups and downs, etc. are some of the major deterrents for high-performance RLC modelled (VLSI) interconnects. This research paper primarily proposes two novel encoding methods (I and II) for RLC modelled interconnects to reduce the effect of crosstalk, simultaneous switching noise (SSN) and power consumption. Design/methodology/approach – The proposed methods are based on the bus encoding method that is effective and well-suited for the reduction of the crosstalk noise. This method encodes or transforms incoming data in a manner that encoded data contain minimum or no crosstalk effects. The proposed encoding method uses the bus invert (BI) method. The proposed encoding methods are able to avoid the worst-case crosstalks while consuming lesser power during transmission in VLSI interconnects. Findings – It is observed that the proposed encoders reduced/eliminated the worst-case crosstalk by reducing SSN. The encoding method I also reduces Type 0 crosstalk by 100 per cent, while Type 1 crosstalk is reduced by 36.4 per cent and Type 2 is reduced by 16.8 per cent. The average simultaneous switching is reduced by 51.1 per cent. Similarly, encoding method II reduces switching activity by 10.3 per cent, whereas the coupling activity is reduced by 35.4 per cent. Furthermore, encoding method II also reduced Type 0, Type 1 and Type 2 crosstalk by 100, 36.9 and 27.1 per cent, respectively. Hence, the proposed encoding methods reduced the worst-case crosstalk completely. Research limitations/implications – In VLSI technology, the reduction in feature size and the increase in operating frequency are quite rapid. This leads to higher propagation delay, crosstalk and power dissipation through the interconnects. Most of the previously proposed encoders/decoders have turned out to be unsuitable for RLC modelled interconnects. Hence, the proposed encoder would be extremely useful for crosstalk reduction in newer operating conditions. Practical implications – The encoding method I identifies the harsh crosstalks, that is Type 0 and Type 1, in the inverted and non-inverted forms of incoming data with respect to the previous data. The data having minimum crosstalk in the inverted and non-inverted forms are only sent through the transmission line. The encoding method I also removes the worst-case crosstalk and simultaneously reduces other mild crosstalks. The removal of worst-case crosstalk improves the overall performance of the interconnect. The encoding method II identifies Type 2 crosstalk along with Type 0 and Type 1 similar to encoding method I. Furthermore, the encoding method II exhibits an improvement over method I in terms of reduction in crosstalk and power dissipation. Originality/value – This paper proposes a novel encoding method to reduce worst-case crosstalk effects that reduces SSN. The proposed encoding methods achieve their purpose of crosstalk reduction for several technology nodes. [ABSTRACT FROM AUTHOR]

Based on transmission line modeling (TLM), and using the Nichols chart, we present a bandwidth and stability analysis, together with step time responses, for coupled multilayer graphene nanoribbon (MLGNR) interconnects that is inquired for the first time. In this analysis, the dependence of the degree of crosstalk relative stability for coupled MLGNR interconnects comprising of both capacitive and mutual-inductive couplings between adjacent MLGNR has been acquired. The obtained results show that with increasing the length or decreasing the width of the MLGNRs, the stability in near-end output increases. While, any increase in the length or width of MLGNRs, decrease the stability of far-end output. Also, by increasing capacitive coupling or decreasing inductive coupling, the near-end output becomes more stable, and the far-end output becomes less stable. Moreover, any increase in the length or capacitive coupling, decreases the bandwidth, whereas any increase in the width or inductive coupling, increases the bandwidth. Finally, transient simulations with Advanced Design System (ADS) show that the model has an excellent accuracy. [ABSTRACT FROM AUTHOR]

Ultra-low power designs extensively exploit the sub-threshold region of operation of Complementary metal-oxide semiconductor (CMOS) circuits. Though sub-threshold circuit operation shows huge potential towards satisfying the ultra-low power requirement, increased crosstalk and delay have become serious design challenges particularly for sub-threshold interconnects. In this paper, novel analytical time-domain models governing the output voltage and crosstalk-induced delay of CMOS gates driving coupled resistive-capacitive interconnect in sub-threshold domain are presented. Subsequently, the transient analysis of simultaneously switching two and three coupled interconnects is carried out. It is demonstrated that the modeling of driver by linear resistance can lead to about 38 % average error in the estimation of propagation delay. The numerical results illustrate that the proposed model quite accurately estimates the performance of coupled on-chip interconnects. An average error of less than 7 % is observed in estimation of waveform shape and delay. [ABSTRACT FROM AUTHOR]

An efficient method for statistically characterizing multiconductor transmission line (MTL) networks subject to a large number of manufacturing uncertainties is presented. The proposed method achieves its efficiency by leveraging a high-dimensional model representation (HDMR) technique that approximates observables (quantities of interest in MTL networks, such as voltages/currents on mission-critical circuits) in terms of iteratively constructed component functions of only the most significant random variables (parameters that characterize the uncertainties in MTL networks, such as conductor locations and widths, and lumped element values). The efficiency of the proposed scheme is further increased using a multielement probabilistic collocation (ME-PC) method to compute the component functions of the HDMR. The ME-PC method makes use of generalized polynomial chaos (gPC) expansions to approximate the component functions, where the expansion coefficients are expressed in terms of integrals of the observable over the random domain. These integrals are numerically evaluated and the observable values at the quadrature/collocation points are computed using a fast deterministic simulator. The proposed method is capable of producing accurate statistical information pertinent to an observable that is rapidly varying across a high-dimensional random domain at a computational cost that is significantly lower than that of gPC or Monte Carlo methods. The applicability, efficiency, and accuracy of the method are demonstrated via statistical characterization of frequency-domain voltages in parallel wire, interconnect, and antenna corporate feed networks. [ABSTRACT FROM PUBLISHER]

In this paper, the crosstalk effects in both small and large diameter multiwalled carbon nanotube bundle interconnects (MWCNTs) for the future nanoscale integrated circuits are studied with the help of ABCD parameter matrix approach for global levels of interconnects at 22- and 14-nm technology nodes. Here, isolated MWCNTs are modeled using an equivalent single conductor transmission line. The simulation results show that the results are at par with the result of SPICE model. It is observed that performance wise, the large diameter MWCNT bundles are better than both small diameter MWCNT bundles and copper wire for both repeated and unrepeated interconnects. The same trend is observed with the number of inserted repeaters. For repeated wires, the optimized placement of repeaters offsets the delay advantage numbers of MWCNT bundles over copper wire. Technology scaling adversely impacts the delay advantage numbers of small diameter MWCNT bundles. As far as the worst-case crosstalk noise peak voltage is concerned, the large diameter MWCNT bundles also outperform both small diameter MWCNT bundles and copper wire for longer interconnects. However, for shorter interconnects, copper wire and small diameter bundles outclass the large diameter bundles due to their relatively larger time constant. We have compared our crosstalk analysis results with the earlier work to justify the validity of our proposed model and observed that the results with our model are in well conformity with the existing work. It is seen that even the tall Cu vias are not going to significantly affect the performance of MWCNT bundle interconnects. Twice the minimum width global level interconnects are the optimal choice to achieve the maximum delay advantage using MWCNT bundle interconnects in comparison with Cu-based interconnects. Finally, our analysis shows that from the performance and signal integrity perspective, the large diameter MWCNT bundles are a suitable alternative to both small diameter MWCNT bundles and copper interconnects for future integrated circuit technology generations. [ABSTRACT FROM PUBLISHER]

In this paper, an analytical framework to model crosstalk in sub-threshold regime of buffer driven coupled interconnects has been presented. Sub-threshold current model is used to represent the transistor. Propagation delay and timing are determined for the conditions when inputs to the coupled interconnect are switching in-phase and out-of-phase. Analytical expressions governing peak noise have also been presented. A comparative analysis of the analytical results with SPICE simulations shows that the proposed models capture waveform shape, propagation delay, timing and noise peaks with good accuracy. It is also analyzed that crosstalk is influenced by variation in the interconnect parameters namely length, width, adjacent spacing and buffer size. [ABSTRACT FROM AUTHOR]

Ultra-low power circuit design has received a wide attention due to the fast growth and prominence of portable battery-operated devices with stringent power constraint. Though sub-threshold circuit operation shows huge potential toward satisfying the ultra-low power requirement, it holds challenging design issues. Of these, the increased crosstalk and delay have become serious challenges, particularly for sub-threshold interconnects as integration density increases with every scaled technology node. Consequently, in this paper an analytical approach providing closed form expressions for dynamic crosstalk in coupled interconnects under sub-threshold condition has been proposed. The proposed model is based on the sub-threshold current-voltage expression for a metal-oxide semiconductor transistor. The model determines the propagation delay and timings of the aggressor and victim drivers for the conditions when inputs are switching in-phase and out-of-phase. Subsequently, the transient analysis of dynamic crosstalk is carried out. The comparison of analytical results with SPICE shows that the model captures waveform shape, propagation delay, and timing with good accuracy, with less than 5 % error in timing estimation. [ABSTRACT FROM AUTHOR]

In this paper, an analytical framework to model crosstalk in sub-threshold regime of buffer driven capacitively coupled interconnects has been carried out. The proposed analytical model captures waveform shape and noise peaks quite efficiently. It is analyzed that crosstalk is influenced by variations in interconnect parameters viz. length, width, adjacent spacing and driver size. A comparative analysis between the proposed analytical model and SPICE results shows a very good agreement. The analytical models yield maximum percentage errors of 5.75 % and 6.32 % for negative and positive noise voltages respectively among all the measured observations. The analysis has been carried out for 65 nm technology node. [ABSTRACT FROM AUTHOR]

In UDSM technology, on-chip interconnect wires form a complex geometry and introduces wire and coupling parasitics. The coupling parasitics ( M, C) introduce crosstalk noise which may lead to critical delays/logic malfunctions. This paper analyzes the dependency of crosstalk noise and delay on coupling parasitics for simultaneously switching inputs using FDTD technique. The FDTD method is used because it is a strong mathematical platform for the analysis of time domain behavior of coupled lines. For implementation of FDTD algorithm, discretizations are carried out in time and space both. To ensure stability in FDTD solution, the discrete voltage points are interlaced by current points in both space and time. To validate the proposed method, FDTD computations are carried out and results are compared with those of conventional SPICE results. A good agreement of FDTD results has been observed with respect to SPICE results. An average error of less than 2 % is observed for the proposed FDTD algorithm with respect to SPICE. [ABSTRACT FROM AUTHOR]

The crosstalk delay associated with global on-chip interconnects becomes more severe in deep submicrometer technology, and hence can greatly affect the overall system performance. Based on a delay model proposed by Sotiriadis , transition patterns over a bus can be classified according to their delays. Using this classification, crosstalk avoidance codes (CACs) have been proposed to alleviate the crosstalk delays by restricting the transition patterns on a bus. In this paper, we first propose a new classification of transition patterns, and then devise a new family of CACs based on this classification. In comparison to the previous classification, our classification has more classes and the delays of its classes do not overlap, both leading to more accurate control of delays. Our new family of CACs includes some previously proposed codes as well as new codes with reduced delays and improved throughput. Thus, this new family of CACs provides a wider variety of tradeoffs between bus delay and efficiency. Finally, since our analytical approach to the classification and CACs treats the technology-dependent parameters as variables, our approach can be easily adapted to a wide variety of technologies. [ABSTRACT FROM PUBLISHER]

The precise design of modern carbon nanoscale interconnects and EMC shields is presented in this paper via a nonstandard locally one-dimensional finite-difference time-domain algorithm. A key attribute of the new generalized technique is its frequency-dependent formulation in conjunction with an accuracy-adjustable meshing process to identify regions of smooth field variation and hence seriously reduce dispersion errors. In this way, the high-order unconditionally-stable method remains fully wideband and generates effective dual grids that allow the consistent analysis of complex carbon nanotube interactions with affordable resources. Numerical simulations, studying the performance features of various demanding applications in a wide frequency range, prove the advantages of the proposed schemes. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power receiver with two-tap decision feedback equalization (DFE) and novel far-end crosstalk (FEXT) cancellation capability, implemented in a 45-nm SOI CMOS process. The receiver employs a half-rate speculative DFE architecture to allow for the use of low-power front-end circuitry and CMOS clock buffers. In the proposed architecture, a switched-capacitor sample-hold at the front-end is employed to perform DFE tap summation. This technique is generalized to implement n taps of equalization. The receiver compensates the effect of crosstalk without making a decision on the received aggressor signal. Due to the low-power nature of the switched-capacitor front-end, the crosstalk cancellation is possible with only 33∼\mu \W/Gbps/lane power overhead. The receiver was tested over channels with different levels of loss and coupling. The signaling rate with \BER< \ 10^-12 was significantly increased with the use of DFE and crosstalk cancellation scheme for highly coupled and lossy PCB traces. The DFE receiver equalizes 15-Gb/s data over a channel with more than 14-dB loss while consuming about 7.5 mW from a 1.2-V supply. At lower data rates it equalizes channels with over 21-dB loss. [ABSTRACT FROM AUTHOR]

In this paper, we proposed BIST-based architecture to at-speed test of crosstalk faults for system-on-chip interconnects. This architecture includes IEEE 1500 wrapper enhanced cells intended for multiple victim test model test patterns generation and analysis test responses. One new instruction is used to control cells and test pattern generator controller in serial test access mechanism of the standard in order to fully comply with conventional IEEE 1500 standard. [ABSTRACT FROM AUTHOR]

Crosstalk effects in multiwall carbon nanotube (MWCNT) interconnects for future ICs are investigated by virtue of the equivalent single conductor model and the finite-difference time-domain solution of transmission line equations. The worst case time delay and the peak crosstalk voltage on victim wire of multiwire MWCNT interconnect configurations are derived and compared to those of the copper (Cu) wire counterparts for the intermediate and global interconnects at the 22- and 14-nm technology nodes. The numerical results illustrate that the crosstalk-induced time delays in the MWCNT interconnects are much smaller than those in the Cu interconnects, in particular, for longer wires. Nevertheless, the MWCNT interconnects exhibit little improvement on the crosstalk-induced noises in comparison with their Cu counterparts. [ABSTRACT FROM AUTHOR]

With the shrink of technology to the nanometer scale, network-on-chip (NOC) has become a reasonable solution for connecting many cores on a single chip. It suffers however from increasingly serious interconnect crosstalk effects, which constrain the overall performance of NOC systems. In this paper, a crosstalk tolerance method is proposed for reducing bus delay on NOC interconnects. Crosstalk-induced latency is predicted by analyzing the possible crosstalk effects of adjacent patterns stored in an NOC router. Transition times of selected bits are then adjusted to relieve these predicted crosstalk-induced effects. Experimental results on interconnects show that the proposed method can achieve the same bus delay reduction as the insertion of extra shielding wires into two adjacent wires, while the proposed method requires no extra wires. Compared with previous methods using a dual rail code, a crosstalk avoidance code, and/or a variable clock, the proposed approach provides a larger reduction of bus delay with less area overhead. [ABSTRACT FROM AUTHOR]

In this paper, the crosstalk problem for carbon nanotubes (CNTs) bundled interconnects is modeled in the framework of the multiconductor transmission line (MTL) theory by using a fluid description of the conduction phenomena in CNTs. Two two-port models for a two-line interconnect (one aggressor and one victim) are proposed. The first is based on the full-MTL equations coupling each CNT in the bundles. The second, which is a reduced order TL model coupling the CNT bundles, is derived from the first one and used for fast computations. The crosstalk models are used to study the impact on relevant electromagnetic performances of some actual technological and design aspects, such as the variability of the number of conducting CNTs in each bundle, their position in the cross section, the proximity of the signaling lines, the cross-sectional aspect ratio, and some advances in CNT manufacturing techniques. Both frequency- and time-domain characteristics are evaluated and compared with those of ideally scaled traditional copper interconnects. The results are compared with those obtained by simplified approaches, showing, in particular, that simple RC models may underestimate the crosstalk. [ABSTRACT FROM PUBLISHER]

This paper proposes two crosstalk-aware signaling techniques based on pulse width modulation (PWM) for energy-efficient on-chip global busses. Two bits of information are encoded into transition type and pulse width for transmission over one wire. The effect of crosstalk on pulses is compensated by pre-correction techniques and self-calibration circuitry mitigates variability. Measurements from 5 mm on-chip links in 65 nm CMOS show that the proposed schemes simultaneously achieve 15% performance improvement, 46% peak energy reduction, up to 25% average energy reduction, and >2X leakage reduction compared to conventional repeaters. Self-calibration of the encoder and decoder circuits against process variation reduced the delay spread of 21 chips by >2.5X. [ABSTRACT FROM PUBLISHER]

This paper presents a delay and crosstalk noise model for coupled resistance-inductance-capacitance (RLC) on-chip interconnects. The proposed algorithm, based on a modified Lie formula, is used to convert the solution of the transmission line network into delay algebraic equations to obtain the time domain response. The proposed algorithm is not limited to fixed number of coupled RLC lines or to specific topologies and can be used to model both identical and nonidentical multiconductor lines and loads. For the example presented in this paper, the 50% delay and crosstalk using the proposed method agrees with SPICE results to within 0.75% average error. [ABSTRACT FROM AUTHOR]

Abstract: With advance in technology and working frequency reaching gigahertz, designing and testing interconnects have become an important issue. In this paper, we proposed a BIST-based boundary scan architecture to at-speed test of crosstalk faults for inter-switch communication links in network on chip. This architecture includes enhanced cells intended for MVT model test patterns generation and analysis test responses. One new instruction is used to control cells and TPG controller in the at-speed test mode in order to fully comply with conventional IEEE 1149.1 standard. [Copyright &y& Elsevier]

This work proposes an accurate crosstalk noise estimation method in the presence of multiple RC lines for use in design automation tools. The method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveform. Noise peak and width expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is 4.1% and for the width is 6.8% while allowing for very fast analysis. [ABSTRACT FROM AUTHOR]

Using physics-based circuit models, the performances of carbon nanotube (CNT) interconnects, both single- and multiwall (SWNT and MWNT), are benchmarked against their copper counterparts at a realistic operating temperature (100 °C). The models used capture various electron phonon scattering mechanisms and the dependence of quantum conductance on temperature and diameter. It is demonstrated that any performance comparison between CNT and copper wires needs to be done at realistic temperatures because changes in temperature affect copper and CNT interconnects quite differently. The results of this paper demonstrate that a hybrid system of copper/SWNT/MWNT offers the highest performance enhancement for interconnects. [ABSTRACT FROM AUTHOR]

With advances in VLSI technology, increasing wire density causes coupled-noise or cross-talk, which may lead to critical delays or logic malfunctions. Traditional SPICE simulators are not time-efficient estimators of crosstalk, hence alternatives are sought to ensure acceptable signal integrity in a limited design cycle time. This work proposes a novel and accurate crosstalk noise estimation method in the presence of multiple lines for use in design automation tools. It offers a complete multiline noise model, for the first time, by representing active and passive aggressors simultaneously on the victim line. In the model, active aggressors are represented by current sources and passive aggressors are accurately modelled as equivalent capacitances. Realistic exponential aggressor waveform and resistive shielding effect is all considered. This approach allows to obtain a general noise model that considers the effect of many active and passive aggressors and general formulas derived can easily be applied to real cases. Results show an average error of 4.4% for the noise peak and 6.8% for the width with respect to HSPICE while allowing for very fast analysis. [ABSTRACT FROM AUTHOR]

Based on physical models, distributed circuit models are presented for single-walled carbon nanotubes (SWCNs) and SWCN bundles that are valid for all voltages and lengths. These models can be used for circuit simulations and compact modeling. It is demonstrated that by customizing SWCN interconnects at the local, semiglobal, and global levels, several major challenges facing gigascale integrated systems can potentially be addressed. For local interconnects, monolayer or multilayer SWCN interconnects can offer up to 50% reduction in capacitance and power dissipation with up to 20% improvement in latency if they are short enough (< 20 μm). For semiglobal interconnects, either latency or power dissipation can be substantially improved if bundles of SWCNs are used. The improvements increase as the cross-sectional dimensions scale down. For global interconnects, bandwidth density can be improved by 40% if there is at least one metallic SWCN per 3-nm² cross-sectional area. [ABSTRACT FROM AUTHOR]