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Low- and high-field transports are investigated for \HfO2-based MOSFETs with ultrathin equivalent oxide thickness (UTEOT) (EOT = \6.4-\8.4\ \\rm\AA) achieved by a remote interface layer (IL) scavenging method. A detailed comparison with a SiON reference demonstrates none of the detrimental effects from \HfO2-related Coulomb nor phonon additional scattering on the high-field velocity. Increased surface roughness may reduce the high-field velocity by 20% for the device with the thinnest IL. This is explained by an increase of the backscattering which reduces the ballistic efficiency for the shortest devices (LMET = \25\ \nm). However, the on-state current (ION) for UTEOT devices has the best performance at a given high-lateral-field velocity. Therefore, EOT scaling remains a valid tool for ION-performance improvement for CMOS scaling also with new architectures and substrates. [ABSTRACT FROM PUBLISHER]

One of the fundamental questions for gate-stack scaling is whether the low-field mobility measured in long-channel devices is a good proxy for short-channel performance at high field. In this paper, we thoroughly investigate low- and high-field transports (velocity and mobility) in 1-nm-EOT high-κ materials on Si (100) and (110) down to cryogenic temperature. It is shown that scattering in Si substrate dominates the transport at high field, thus enabling relaxation of the low-field-mobility requirement for future scaling below 1-nm EOT. [ABSTRACT FROM AUTHOR]

In this paper, we study the mobility and dielectric quality of MOSFETs with 1-nm Equivalent Oxide Thickness (EOT) grown on substrates with different crystallographic orientations: (100) and (110). Measurement techniques based on RF split CVs (150 MHz) on short-channel devices (down to 80 nm) are used to extract the electrical parameters. Despite the different oxidation growth rates expected by changing the substrate orientation, we obtain similar EOT values even for thin dielectrics (1 nm). Further identical gate overlaps are found regardless of the substrate orientation. The mobility in (110) substrate shows a large improvement for p-MOS. This improvement is independent of the EOT (down to 1 nm) and the length scaling. Although larger interface states were observed by charge pumping for the (110) devices, low-temperature mobility study suggests that the remote charge scattering, and therefore, the gate stack quality is the same. [ABSTRACT FROM AUTHOR]