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Inspired by the behaviour of biological receptive fields and the human visual system, a network model based on spiking neurons is proposed to detect edges in a visual image. The structure and the properties of the network are detailed in this paper. Simulation results show that the network based on spiking neurons is able to perform edge detection within a time interval of 100 ms. This processing time is consistent with the human visual system. A firing rate map recorded in the simulation is comparable to Sobel and Canny edge graphics. In addition, the network can separate different edges using synapse plasticity, and the network provides an attention mechanism in which edges in an attention area can be enhanced. [ABSTRACT FROM AUTHOR]

The naïve Bayes classifier has been widely applied to decision-making or classification. Because the naïve Bayes classifier prefers to dealing with discrete values, an novel discretization approach is proposed to improve naïve Bayes classifier and enhance decision accuracy in this paper. Based on the statistical information of the naïve Bayes classifier, a distributional index is defined in the new discretization approach. The distributional index can be applied to find a good solution for discretization of continuous attributes so that the naïve Bayes classifier can reach high decision accuracy for instance information systems with continuous attributes. The experimental results on benchmark data sets show that the naïve Bayes classifier with the new discretizer can reach higher accuracy than the C5.0 tree. Keywords: Decision-making, Classification, Naive Bayes Cassifier, Discretizer. [ABSTRACT FROM AUTHOR]

This paper presents a hardware implementation of a Time Multiplexing Architecture (TMA) that can interconnect arrays of neurons in an Artificial Neural Network (ANN) using a single metal wire. The approach exploits the relative slow operational speed of the biological system by using fast digital hardware to sequentially sample neurons in a layer and transmit the associated spikes to neurons in other layers. The motivation for this work is to develop minimal area inter-neuron communication hardware. An estimate of the density of on-chip neurons afforded by this approach is presented. The paper verifies the operation of the TMA and investigates pulse transmission errors as a function of the sampling rate. Simulations using the Xilinx System Generator (XSG) package demonstrate that the effect of these errors on the performance of an SNN, pre-trained to solve the XOR problem, is negligible if the sampling frequency is sufficiently high. [ABSTRACT FROM AUTHOR]

The current growth of neuron technology is reflected by the increasing focus on this research area within the European research community. One topic is the implementation of neural networks (NNs) onto silicon. FPGAs provide an excellent platform for such implementations. The development of NNs has led to multiple abstractions for various generations. The different demands that each generation pose, present different design challenges. This has left ambiguous decisions for the neuroengineer into what model to implement. The authors have undertaken an investigation into four commonly selected neuron models, two classical models and two formal spike models. A software classification problem is combined with hardware resource requirements for FPGAs, implemented utilising a novel design flow. This provides an overall comparative analysis to be made and identification of the most suitable model to implement on an FPGA. [ABSTRACT FROM AUTHOR]