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This paper presents a new method for diagnosing (detection and location) multiple faults in an application-dependent interconnect of a SRAM-based FPGA. For fault detection, the proposed technique retains the original interconnect configuration and modifies the function of the LUTs using the new LUT programming function 1-Bit Sum Function (1-BSF); in addition, it utilizes features such as branches in the nets as well as the primary (unused) IOs of the FPGAs. The proposed method detects all possible stuck-at and bridging faults of all cardinalities in a single configuration; fault detection requires 1 + log2k test configurations for multiple stuck-at location and 2 + 2log2k additional test configurations to locate more than one pair-wise bridging faults (where k denotes the maximum combinational depth of the FPGA circuit). Following detection, the locations of multiple faults are hierarchically identified using the walking-1 test set and an adaptive approach for the interconnect structure. Net ordering independence is accomplished by utilizing features such as the presence of paths of nets that are either disjoint or joint between the primary input and at least one primary output. As validated by simulation on benchmark circuits, the proposed method scales extremely well for different Virtex FPGA families; this results in a significant reduction in the number of configurations for diagnosing multiple faults. [ABSTRACT FROM AUTHOR]

Abstract: This paper proposes a new fine grain fault diagnosis method for the interconnect of an arbitrary design implemented in a Field Programmable Gate Array (FPGA). In the proposed method, interconnect faults detected at the primary output are back-tracked until the faulty nets are precisely located. This is carried out by programming the LUTs on the faulty path to be transparent and thus propagating the value of a specific net under test to the primary output for verification against the expected value of the net. After every back-tracking iteration, the fault location is narrowed down and thus the number of nets to be tested decreases significantly. Therefore, the upper bound of the number of configurations (NMAX ) required to locate a faulty net, depends on the maximum combinational depth (DCOMB ) of the circuit, and it is approximately equivalent to three times of DCOMB . The proposed method has the ability to locate multiple faults without any fault masking with fault coverage that includes all possible stuck-at, open and pair-wise bridging faults. The proposed method is validated on the ISCAS’89 benchmark circuits mapped on Xilinx Spartan 3E, Virtex-4 and Virtex-5 FPGAs and the results are presented. The simulation results show that applying the proposed method on circuits with less combinational depth reduces the required number of test configurations on average by 35% when compared with the latest method available in the literature. [Copyright &y& Elsevier]