As growing complexity of digital VLSI circuits, fault detection and correction processes have been the most crucial phases during IC design. Many CAD tools and formal approaches have been used for debugging and localizing different kinds of design bugs. However, the search space explosion problem remains the main problem for IC designers. Recently, Artificial intelligence and machine learning models have been expanded in feature extraction and reduction models. In this paper, we introduce a new fault detection model based on deep learning for extracting features and detecting faults from large-sized digital circuits. The main goal of the proposed model is to avoid the search space using stacked sparse autoencoder, a specific type of artificial neural network. The model consists of three phases: test pattern generation using ATALANTA software, feature reduction using SSAE and classification for fault detection. Test vectors are utilized in SSAE as a training data for unsupervised learning phase. The performance of feature extraction is tested by changing the architecture of SSAE network and sparsity constraint. The proposed algorithm has been implemented using eight combinational digital circuits from ISCAS'85. From experimental results, the maximum fault coverage using ATALANTA tool delivers around 99.2% using ISCAS'85. In addition, the maximum validation accuracy of proposed SSAE model delivers around 99.7% in feature reduction phase. [ABSTRACT FROM AUTHOR]