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A 30-MHz voltage-mode buck converter using a delay-line-based pulse-width-modulation controller is proposed in this brief. Two voltage-to-delay cells are used to convert the voltage difference to delay-time difference. A charge pump is used to charge or discharge the loop filter, depending on whether the feedback voltage is larger or smaller than the reference voltage. A delay-line-based voltage-to-duty-cycle (V2D) controller is used to replace the classical ramp-comparator-based V2D controller to achieve wide duty cycle. A type-II compensator is implemented in this design with a capacitor and resistor in the loop filter. The prototype buck converter was fabricated using a 0.18- ${\mu }\text{m}$ CMOS process. It occupies an active area of 0.834 mm2 including the testing PADs. The tunable duty cycle ranges from 11.9%–86.3%, corresponding to 0.4 V–2.8 V output voltage with 3.3 V input. With a step of 400 mA in the load current, the settling time is around 3 ${\mu }\text{s}$. The peak efficiency is as high as 90.2% with 2.4 V output and the maximum load current is 800 mA. [ABSTRACT FROM AUTHOR]

Without using bipolar transistors, serially connected inverter cells generate clock delay according to temperature. The delay is compared with a reference clock to estimate the temperature. The proposed time-to-digital converter (TDC) structure is using a time-domain delta–sigma $(\Delta\Sigma)$ modulator. This type of TDC with \Delta\Sigma$ modulator can achieve higher resolution by increasing the oversampling ratio, with the advantages of low area and low power consumption. To increase the accuracy by producing true temperature-independent time delay, an external reference clock is utilized, instead of temperature-independent inverter cells, for robust operations. The measured temperature sensors demonstrated a minimum power consumption of 480 nW and a resolution under 0.1 °C. The 3\sigma$ error of the sensor is ±0.99 °C over −20 °C–80 °C temperature range from ten-sample measurement results. The chip area is 0.089 mm2 using a Dongbu 0.18- CMOS process. The conversion rate is 1.25 samples/s. [ABSTRACT FROM PUBLISHER]