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Multiple second-order generalized integrators (MSOGI) has been widely used to extract the signal that contains multiple harmonics. The MSOGI needs to be implemented in the discrete-time domain for its practical applications. More critically, the discretization method can greatly affect its performance. The existing discretization methods for MSOGI can be divided into three categories: entire transfer-function discretization, SOGI-transfer-function discretization, and integrator discretization. The theoretical analysis indicates that the first method can avoid the errors caused by unit delay, but it is hard to be digitally realized for high-order transfer functions. The other two methods have nonnegligible errors in both the phase and the quadrature characteristic due to the unit delay. In this letter, we propose a novel discretization method by modifying the structure of integrator discretization. This method can enhance the performance in both the phase and the quadrature characteristic with an acceptable computation burden, which has been theoretically analyzed and experimentally verified. [ABSTRACT FROM AUTHOR]

The dead-time elimination pulsewidth modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead time and essentially avoiding the dead-time effect in power converters. However, the current zero crossing will be distorted by the current jump generated by the drive-pulse alternation, and the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is, therefore, proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pulses to smooth the current jump at zero crossing, and a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments, respectively, in the unbalanced-current, power-change, and frequency-variation conditions with an RL load, as well as in a grid-connected converter. [ABSTRACT FROM AUTHOR]