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We have devised a digital time-division multiplexing (TDM) scheme for minimizing the circuit complexity required for an array of sensors. As a proof-of-concept, we have designed, fabricated, and tested a four-channel digital TDM readout circuit. The proposed scheme can be generalized for a larger number of channels. The readout circuit comprises an array of ADCs to digitize sensor outputs, a multiplexing unit, a clock controller, and a counter with parallel-to-serial output interface. For demonstration purposes, we employed low-pass phase modulation–demodulation ADCs running in a synchronous mode of operation. To facilitate an independent verification of circuit operation, we also placed an on-chip pattern generator to apply a unique pattern to each channel. The multiplexing unit is based on an array of sequentially triggered switches, each controlling the flow of data from a single ADC to a common output bus. In our scheme, the switches are realized using RS-flip-flops with nondestructive (RSN) readout cells with only one RSN cell turned on at a time. Multiplexed output data were stored in ripple counter based on T-flip-flops and read out to room temperature electronics using a serial interface. The chip was immersed in liquid helium at 4.2-K temperature and extensively evaluated at sampling frequencies up to 12.8 GHz. By means of embedded pattern generators, we proved the correct operation of each channel and of all four channels combined. We also were able to perform reconstruction of a signal applied to individual ADC. The chip was fabricated using HYPRES’ 4.5-kA/cm2 process with four Nb metal layers. We briefly discuss the proposed scheme's scalability for higher current density and smaller feature size fab processes. [ABSTRACT FROM PUBLISHER]